[MIR] Serialize virtual register flags

llvm/include/llvm/CodeGen/MIRParser/MIParser.h

@@ -37,16 +37,15 @@ class TargetRegisterClass;
 class TargetSubtargetInfo;
 
 struct VRegInfo {
-  enum uint8_t {
-    UNKNOWN, NORMAL, GENERIC, REGBANK
-  } Kind = UNKNOWN;
+  enum : uint8_t { UNKNOWN, NORMAL, GENERIC, REGBANK } Kind = UNKNOWN;
   bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
   union {
     const TargetRegisterClass *RC;
     const RegisterBank *RegBank;
   } D;
   Register VReg;
   Register PreferredReg;
+  std::vector<uint8_t> Flags;
 };
 
 using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
@@ -150,6 +149,8 @@ struct PerTargetMIParsingState {
   /// Return null if the name isn't a register bank.
   const RegisterBank *getRegBank(StringRef Name);
 
+  bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const;
+
   PerTargetMIParsingState(const TargetSubtargetInfo &STI)
     : Subtarget(STI) {
     initNames2RegClasses();

llvm/include/llvm/CodeGen/MIRYamlMapping.h

@@ -191,6 +191,7 @@ struct VirtualRegisterDefinition {
   UnsignedValue ID;
   StringValue Class;
   StringValue PreferredRegister;
+  std::vector<FlowStringValue> RegisterFlags;
 
   // TODO: Serialize the target specific register hints.
 
@@ -206,6 +207,8 @@ template <> struct MappingTraits<VirtualRegisterDefinition> {
     YamlIO.mapRequired("class", Reg.Class);
     YamlIO.mapOptional("preferred-register", Reg.PreferredRegister,
                        StringValue()); // Don't print out when it's empty.
+    YamlIO.mapOptional("flags", Reg.RegisterFlags,
+                       std::vector<FlowStringValue>());
   }
 
   static const bool flow = true;

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -1213,6 +1213,15 @@ class TargetRegisterInfo : public MCRegisterInfo {
   virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const {
     return false;
   }
+
+  virtual std::optional<uint8_t> getVRegFlagValue(StringRef Name) const {
+    return {};
+  }
+
+  virtual SmallVector<StringLiteral>
+  getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const {
+    return {};
+  }
 };
 
 //===----------------------------------------------------------------------===//

llvm/lib/CodeGen/MIRParser/MIParser.cpp

@@ -127,6 +127,16 @@ bool PerTargetMIParsingState::getRegisterByName(StringRef RegName,
   return false;
 }
 
+bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName,
+                                               uint8_t &FlagValue) const {
+  const auto *TRI = Subtarget.getRegisterInfo();
+  std::optional<uint8_t> FV = TRI->getVRegFlagValue(FlagName);
+  if (!FV)
+    return true;
+  FlagValue = *FV;
+  return false;
+}
+
 void PerTargetMIParsingState::initNames2InstrOpCodes() {
   if (!Names2InstrOpCodes.empty())
     return;

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

@@ -696,6 +696,15 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
                                  VReg.PreferredRegister.Value, Error))
         return error(Error, VReg.PreferredRegister.SourceRange);
     }
+
+    for (const auto &FlagStringValue : VReg.RegisterFlags) {
+      uint8_t FlagValue;
+      if (Target->getVRegFlagValue(FlagStringValue.Value, FlagValue))
+        return error(FlagStringValue.SourceRange.Start,
+                     Twine("use of undefined register flag '") +
+                         FlagStringValue.Value + "'");
+      Info.Flags.push_back(FlagValue);
+    }
   }
 
   // Parse the liveins.

llvm/lib/CodeGen/MIRPrinter.cpp

@@ -113,7 +113,8 @@ class MIRPrinter {
 
   void print(const MachineFunction &MF);
 
-  void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
+  void convert(yaml::MachineFunction &YamlMF, const MachineFunction &MF,
+               const MachineRegisterInfo &RegInfo,
                const TargetRegisterInfo *TRI);
   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
                const MachineFrameInfo &MFI);
@@ -231,7 +232,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
   YamlMF.NoVRegs = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::NoVRegs);
 
-  convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
+  convert(YamlMF, MF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   MachineModuleSlotTracker MST(MMI, &MF);
   MST.incorporateFunction(MF.getFunction());
   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
@@ -316,10 +317,21 @@ printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
   }
 }
 
-void MIRPrinter::convert(yaml::MachineFunction &MF,
+static void printRegFlags(Register Reg,
+                          std::vector<yaml::FlowStringValue> &RegisterFlags,
+                          const MachineFunction &MF,
+                          const TargetRegisterInfo *TRI) {
+  auto FlagValues = TRI->getVRegFlagsOfReg(Reg, MF);
+  for (auto &Flag : FlagValues) {
+    RegisterFlags.push_back(yaml::FlowStringValue(Flag.str()));
+  }
+}
+
+void MIRPrinter::convert(yaml::MachineFunction &YamlMF,
+                         const MachineFunction &MF,
                          const MachineRegisterInfo &RegInfo,
                          const TargetRegisterInfo *TRI) {
-  MF.TracksRegLiveness = RegInfo.tracksLiveness();
+  YamlMF.TracksRegLiveness = RegInfo.tracksLiveness();
 
   // Print the virtual register definitions.
   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
@@ -332,7 +344,8 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
     Register PreferredReg = RegInfo.getSimpleHint(Reg);
     if (PreferredReg)
       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
-    MF.VirtualRegisters.push_back(VReg);
+    printRegFlags(Reg, VReg.RegisterFlags, MF, TRI);
+    YamlMF.VirtualRegisters.push_back(VReg);
   }
 
   // Print the live ins.
@@ -341,7 +354,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
     printRegMIR(LI.first, LiveIn.Register, TRI);
     if (LI.second)
       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
-    MF.LiveIns.push_back(LiveIn);
+    YamlMF.LiveIns.push_back(LiveIn);
   }
 
   // Prints the callee saved registers.
@@ -353,7 +366,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
       printRegMIR(*I, Reg, TRI);
       CalleeSavedRegisters.push_back(Reg);
     }
-    MF.CalleeSavedRegisters = CalleeSavedRegisters;
+    YamlMF.CalleeSavedRegisters = CalleeSavedRegisters;
   }
 }
 

llvm/test/CodeGen/AMDGPU/limit-coalesce.mir

@@ -2,13 +2,13 @@
 
 # Check that coalescer does not create wider register tuple than in source
 
-# CHECK:  - { id: 2, class: vreg_64, preferred-register: '' }
-# CHECK:  - { id: 3, class: vreg_64, preferred-register: '' }
-# CHECK:  - { id: 4, class: vreg_64, preferred-register: '' }
-# CHECK:  - { id: 5, class: vreg_96, preferred-register: '' }
-# CHECK:  - { id: 6, class: vreg_96, preferred-register: '' }
-# CHECK:  - { id: 7, class: vreg_128, preferred-register: '' }
-# CHECK:  - { id: 8, class: vreg_128, preferred-register: '' }
+# CHECK:  - { id: 2, class: vreg_64, preferred-register: '', flags: [  ] }
+# CHECK:  - { id: 3, class: vreg_64, preferred-register: '', flags: [  ] }
+# CHECK:  - { id: 4, class: vreg_64, preferred-register: '', flags: [  ] }
+# CHECK:  - { id: 5, class: vreg_96, preferred-register: '', flags: [  ] }
+# CHECK:  - { id: 6, class: vreg_96, preferred-register: '', flags: [  ] }
+# CHECK:  - { id: 7, class: vreg_128, preferred-register: '', flags: [  ] }
+# CHECK:  - { id: 8, class: vreg_128, preferred-register: '', flags: [  ] }
 # No more registers shall be defined
 # CHECK-NEXT: liveins:
 # CHECK:    FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %4,

llvm/test/CodeGen/MIR/Generic/register-flag-error.mir

@@ -0,0 +1,13 @@
+# RUN: not llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR
+
+---
+name:  flags
+registers:
+  - { id: 0, class: _, flags: [ 'VFLAG_ERR' ] }
+body: |
+  bb.0:
+    liveins: $w0
+    %0 = G_ADD $w0, $w0
+...
+# ERR: use of undefined register flag
+# ERR: VFLAG_ERR

llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir

@@ -14,8 +14,8 @@ name:            test
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
-  # CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
-  # CHECK: - { id: 2, class: gr32, preferred-register: '$edi' }
+  # CHECK: - { id: 1, class: gr32, preferred-register: '%0', flags: [  ] }
+  # CHECK: - { id: 2, class: gr32, preferred-register: '$edi', flags: [  ] }
   - { id: 1, class: gr32, preferred-register: '%0' }
   - { id: 2, class: gr32, preferred-register: '$edi' }
 body: |

llvm/test/CodeGen/MIR/X86/generic-instr-type.mir

@@ -18,11 +18,11 @@
 ---
 name:            test_vregs
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '', flags: [  ] }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '', flags: [  ] }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '', flags: [  ] }
+# CHECK-NEXT:   - { id: 3, class: _, preferred-register: '', flags: [  ] }
+# CHECK-NEXT:   - { id: 4, class: _, preferred-register: '', flags: [  ] }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }

llvm/test/CodeGen/MIR/X86/register-operand-class.mir

@@ -6,11 +6,11 @@
 ---
 # CHECK-LABEL: name: func
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK:   - { id: 1, class: gr64, preferred-register: '' }
-# CHECK:   - { id: 2, class: gr32, preferred-register: '' }
-# CHECK:   - { id: 3, class: gr16, preferred-register: '' }
-# CHECK:   - { id: 4, class: _, preferred-register: '' }
+# CHECK:   - { id: 0, class: gr32, preferred-register: '', flags: [   ] }
+# CHECK:   - { id: 1, class: gr64, preferred-register: '', flags: [   ] }
+# CHECK:   - { id: 2, class: gr32, preferred-register: '', flags: [   ] }
+# CHECK:   - { id: 3, class: gr16, preferred-register: '', flags: [   ] }
+# CHECK:   - { id: 4, class: _, preferred-register: '', flags: [   ] }
 name: func
 body: |
   bb.0:

llvm/test/CodeGen/MIR/X86/roundtrip.mir

@@ -2,8 +2,8 @@
 ---
 # CHECK-LABEL: name: func0
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK:   - { id: 0, class: gr32, preferred-register: '', flags: [   ] }
+# CHECK:   - { id: 1, class: gr32, preferred-register: '', flags: [   ] }
 # CHECK: body: |
 # CHECK:   bb.0:
 # CHECK:     %0:gr32 = MOV32r0 implicit-def $eflags

llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir

@@ -15,9 +15,9 @@
 name:            test
 tracksRegLiveness: true
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gr32, preferred-register: '$esi' }
-# CHECK-NEXT:  - { id: 2, class: gr32, preferred-register: '$edi' }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '', flags: [   ] }
+# CHECK-NEXT:  - { id: 1, class: gr32, preferred-register: '$esi', flags: [   ] }
+# CHECK-NEXT:  - { id: 2, class: gr32, preferred-register: '$edi', flags: [   ] }
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32, preferred-register: '$esi' }

llvm/test/CodeGen/MIR/X86/virtual-registers.mir

@@ -33,9 +33,9 @@
 name:            bar
 tracksRegLiveness: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '', flags: [   ] }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '', flags: [   ] }
+# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: '', flags: [   ] }
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
@@ -67,9 +67,9 @@ name:            foo
 tracksRegLiveness: true
 # CHECK: name: foo
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '', flags: [   ] }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '', flags: [   ] }
+# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: '', flags: [   ] }
 registers:
   - { id: 2, class: gr32 }
   - { id: 0, class: gr32 }

llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir

@@ -26,9 +26,9 @@ alignment:       16
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '', flags: [   ] }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -56,9 +56,9 @@ alignment:       16
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '', flags: [   ] }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -86,9 +86,9 @@ alignment:       16
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '', flags: [   ] }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }

llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir

@@ -26,9 +26,9 @@ alignment:       16
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '', flags: [   ] }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -56,9 +56,9 @@ alignment:       16
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '', flags: [   ] }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -86,9 +86,9 @@ alignment:       16
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: '', flags: [   ] }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: '', flags: [   ] }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }