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[ARM][AArch64] Introduce the Armv9.6-A architecture version #110825

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Merged
merged 2 commits into from
Oct 4, 2024
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[ARM][AArch64] Introduce the Armv9.6-A architecture version #110825

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38c442a
Introduce the Armv9.6-A architecture version
jthackray Sep 27, 2024
4554e4a
fixup! Introduce the Armv9.6-A architecture version
jthackray Oct 2, 2024
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11 changes: 11 additions & 0 deletions clang/lib/Basic/Targets/AArch64.cpp
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Expand Up @@ -373,6 +373,12 @@ void AArch64TargetInfo::getTargetDefinesARMV95A(const LangOptions &Opts,
getTargetDefinesARMV94A(Opts, Builder);
}

void AArch64TargetInfo::getTargetDefinesARMV96A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Armv9.6-A does not have a v8.* equivalent, but is a superset of v9.5-A.
getTargetDefinesARMV95A(Opts, Builder);
}

void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
Expand Down Expand Up @@ -657,6 +663,8 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
getTargetDefinesARMV94A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_5A)
getTargetDefinesARMV95A(Opts, Builder);
else if (*ArchInfo == llvm::AArch64::ARMV9_6A)
getTargetDefinesARMV96A(Opts, Builder);

// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8|16) builtins work.
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Expand Down Expand Up @@ -1044,6 +1052,9 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
if (Feature == "+v9.5a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_5A.Version)
ArchInfo = &llvm::AArch64::ARMV9_5A;
if (Feature == "+v9.6a" &&
ArchInfo->Version < llvm::AArch64::ARMV9_6A.Version)
ArchInfo = &llvm::AArch64::ARMV9_6A;
if (Feature == "+v8r")
ArchInfo = &llvm::AArch64::ARMV8R;
if (Feature == "+fullfp16") {
Expand Down
2 changes: 2 additions & 0 deletions clang/lib/Basic/Targets/AArch64.h
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Expand Up @@ -148,6 +148,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
MacroBuilder &Builder) const;
void getTargetDefinesARMV95A(const LangOptions &Opts,
MacroBuilder &Builder) const;
void getTargetDefinesARMV96A(const LangOptions &Opts,
MacroBuilder &Builder) const;
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;

Expand Down
4 changes: 4 additions & 0 deletions clang/lib/Basic/Targets/ARM.cpp
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Expand Up @@ -228,6 +228,8 @@ StringRef ARMTargetInfo::getCPUAttr() const {
return "9_4A";
case llvm::ARM::ArchKind::ARMV9_5A:
return "9_5A";
case llvm::ARM::ArchKind::ARMV9_6A:
return "9_6A";
case llvm::ARM::ArchKind::ARMV8MBaseline:
return "8M_BASE";
case llvm::ARM::ArchKind::ARMV8MMainline:
Expand Down Expand Up @@ -891,6 +893,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
case llvm::ARM::ArchKind::ARMV9_3A:
case llvm::ARM::ArchKind::ARMV9_4A:
case llvm::ARM::ArchKind::ARMV9_5A:
case llvm::ARM::ArchKind::ARMV9_6A:
// Filter __arm_cdp, __arm_ldcl, __arm_stcl in arm_acle.h
FeatureCoprocBF = FEATURE_COPROC_B1 | FEATURE_COPROC_B3;
break;
Expand Down Expand Up @@ -1060,6 +1063,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
case llvm::ARM::ArchKind::ARMV9_3A:
case llvm::ARM::ArchKind::ARMV9_4A:
case llvm::ARM::ArchKind::ARMV9_5A:
case llvm::ARM::ArchKind::ARMV9_6A:
getTargetDefinesARMV83A(Opts, Builder);
break;
}
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2 changes: 2 additions & 0 deletions clang/test/CodeGen/arm-acle-coproc.c
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Expand Up @@ -25,6 +25,7 @@
// RUN: %clang_cc1 -triple armv9.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple armv9.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple armv9.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple armv9.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv4 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s
// RUN: %clang_cc1 -triple thumbv4t %s -E -dD -o - | FileCheck --check-prefix=CHECK-V4-THUMB %s
// RUN: %clang_cc1 -triple thumbv5 %s -E -dD -o - | FileCheck --check-prefix=CHECK-V5-THUMB %s
Expand Down Expand Up @@ -54,6 +55,7 @@
// RUN: %clang_cc1 -triple thumbv9.3a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv9.4a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv9.5a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv9.6a %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8 %s
// RUN: %clang_cc1 -triple thumbv8m.base %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-BASE %s
// RUN: %clang_cc1 -triple thumbv8m.main %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-MAIN %s
// RUN: %clang_cc1 -triple thumbv8.1m.main %s -E -dD -o - | FileCheck --check-prefix=CHECK-V8-MAIN %s
Expand Down
19 changes: 19 additions & 0 deletions clang/test/Driver/aarch64-v96a.c
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@@ -0,0 +1,19 @@
// ===== Base v9.6a architecture =====

// RUN: %clang -target aarch64 -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
// RUN: %clang -target aarch64 -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A %s
// GENERICV96A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"

// RUN: %clang -target aarch64_be -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
// RUN: %clang -target aarch64_be -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
// RUN: %clang -target aarch64 -mbig-endian -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
// RUN: %clang -target aarch64 -mbig-endian -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV96A-BE %s
// GENERICV96A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.6a"
//
// ===== Features supported on aarch64 =====
17 changes: 17 additions & 0 deletions clang/test/Driver/arm-cortex-cpus-1.c
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Expand Up @@ -495,3 +495,20 @@
// RUN: %clang -target arm -march=armebv9.5a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V95A %s
// RUN: %clang -target arm -march=armebv9.5-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V95A %s
// CHECK-BE-V95A: "-cc1"{{.*}} "-triple" "armebv9.5{{.*}}" "-target-cpu" "generic"
//
// RUN: %clang -target armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V96A %s
// RUN: %clang -target arm -march=armv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V96A %s
// RUN: %clang -target arm -march=armv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V96A %s
// RUN: %clang -target arm -march=armv9.6a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V96A %s
// RUN: %clang -target armv9.6a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V96A %s
// RUN: %clang -target arm -march=armv9.6a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V96A %s
// RUN: %clang -target arm -mlittle-endian -march=armv9.6-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V96A %s
// CHECK-V96A: "-cc1"{{.*}} "-triple" "armv9.6{{.*}}" "-target-cpu" "generic"

// RUN: %clang -target armebv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V96A %s
// RUN: %clang -target armv9.6a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V96A %s
// RUN: %clang -target armeb -march=armebv9.6a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V96A %s
// RUN: %clang -target armeb -march=armebv9.6-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V96A %s
// RUN: %clang -target arm -march=armebv9.6a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V96A %s
// RUN: %clang -target arm -march=armebv9.6-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V96A %s
// CHECK-BE-V96A: "-cc1"{{.*}} "-triple" "armebv9.6{{.*}}" "-target-cpu" "generic"
2 changes: 2 additions & 0 deletions clang/test/Preprocessor/aarch64-target-features.c
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Expand Up @@ -213,6 +213,7 @@
// RUN: %clang -target aarch64-none-linux-gnu -march=armv9.3-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2 %s
// RUN: %clang -target aarch64-none-linux-gnu -march=armv9.4-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2 %s
// RUN: %clang -target aarch64-none-linux-gnu -march=armv9.5-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2 %s
// RUN: %clang -target aarch64-none-linux-gnu -march=armv9.6-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2 %s
// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2 %s
// CHECK-SVE2: __ARM_FEATURE_FP16_SCALAR_ARITHMETIC 1
// CHECK-SVE2: __ARM_FEATURE_FP16_VECTOR_ARITHMETIC 1
Expand Down Expand Up @@ -671,6 +672,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.6-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
// CHECK-V83-OR-LATER: __ARM_FEATURE_COMPLEX 1
Expand Down
5 changes: 5 additions & 0 deletions clang/test/Preprocessor/arm-target-features.c
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Expand Up @@ -902,6 +902,11 @@
// CHECK-V95A: #define __ARM_ARCH_9_5A__ 1
// CHECK-V95A: #define __ARM_ARCH_PROFILE 'A'

// RUN: %clang -target armv9.6a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V96A %s
// CHECK-V96A: #define __ARM_ARCH 9
// CHECK-V96A: #define __ARM_ARCH_9_6A__ 1
// CHECK-V96A: #define __ARM_ARCH_PROFILE 'A'

// RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
// CHECK-SOFTVFP-NOT: #define __ARM_FP 0x

Expand Down
6 changes: 3 additions & 3 deletions llvm/include/llvm/TargetParser/AArch64TargetParser.h
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Expand Up @@ -118,9 +118,9 @@ struct ArchInfo {
// Defines the following partial order, indicating when an architecture is
// a superset of another:
//
// v9.5a > v9.4a > v9.3a > v9.2a > v9.1a > v9a;
// v v v v v
// v8.9a > v8.8a > v8.7a > v8.6a > v8.5a > v8.4a > ... > v8a;
// v9.6a > v9.5a > v9.4a > v9.3a > v9.2a > v9.1a > v9a;
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Is it worth adding a "v9.6a+" here so that we don't need to keep updating it in the future?

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Good idea. I probably won't do it for this PR, but I'll think about how to simplify the ASCII art.

// v v v v v
// v8.9a > v8.8a > v8.7a > v8.6a > v8.5a > v8.4a > ... > v8a;
//
// v8r has no relation to anything. This is used to determine which
// features to enable for a given architecture. See
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5 changes: 5 additions & 0 deletions llvm/include/llvm/TargetParser/ARMTargetParser.def
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Expand Up @@ -182,6 +182,11 @@ ARM_ARCH("armv9.5-a", ARMV9_5A, "9.5-A", "+v9.5a", ARMBuildAttrs::CPUArch::v9_A,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
ARM_ARCH("armv9.6-a", ARMV9_6A, "9.6-A", "+v9.6a", ARMBuildAttrs::CPUArch::v9_A,
FK_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
ARM_ARCH("armv8-r", ARMV8R, "8-R", "+v8r", ARMBuildAttrs::CPUArch::v8_R,
FK_FPV5_SP_D16,
(ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/TargetParser/Triple.h
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Expand Up @@ -110,6 +110,7 @@ class Triple {
enum SubArchType {
NoSubArch,

ARMSubArch_v9_6a,
ARMSubArch_v9_5a,
ARMSubArch_v9_4a,
ARMSubArch_v9_3a,
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/AArch64/AArch64Features.td
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Expand Up @@ -518,6 +518,11 @@ def FeaturePAuthLR : ExtensionWithMArch<"pauth-lr", "PAuthLR", "FEAT_PAuth_LR",
def FeatureTLBIW : ExtensionWithMArch<"tlbiw", "TLBIW", "FEAT_TLBIW",
"Enable Armv9.5-A TLBI VMALL for Dirty State">;

//===----------------------------------------------------------------------===//
// Armv9.6 Architecture Extensions
//===----------------------------------------------------------------------===//


//===----------------------------------------------------------------------===//
// Other Features
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -827,6 +832,9 @@ def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a",
def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",
[HasV9_4aOps, FeatureCPA],
!listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT, FeatureFAMINMAX])>;
def HasV9_6aOps : Architecture64<9, 6, "a", "v9.6a",
[HasV9_5aOps],
!listconcat(HasV9_5aOps.DefaultExts, [])>;
def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",
[ //v8.1
FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2,
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Expand Up @@ -3771,6 +3771,8 @@ static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
Str += "ARMv9.4a";
else if (FBS[AArch64::HasV9_5aOps])
Str += "ARMv9.5a";
else if (FBS[AArch64::HasV9_6aOps])
Str += "ARMv9.6a";
else if (FBS[AArch64::HasV8_0rOps])
Str += "ARMv8r";
else {
Expand Down
13 changes: 12 additions & 1 deletion llvm/lib/Target/ARM/ARMArchitectures.td
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Expand Up @@ -285,7 +285,18 @@ def ARMv95a : Architecture<"armv9.5-a", "ARMv95a", [HasV9_5aOps,
FeatureCRC,
FeatureRAS,
FeatureDotProd]>;

def ARMv96a : Architecture<"armv9.6-a", "ARMv96a", [HasV9_6aOps,
FeatureAClass,
FeatureDB,
FeatureFPARMv8,
FeatureNEON,
FeatureDSP,
FeatureTrustZone,
FeatureMP,
FeatureVirtualization,
FeatureCRC,
FeatureRAS,
FeatureDotProd]>;
def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,
FeatureRClass,
FeatureDB,
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5 changes: 5 additions & 0 deletions llvm/lib/Target/ARM/ARMFeatures.td
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Expand Up @@ -706,6 +706,11 @@ def HasV9_5aOps : SubtargetFeature<"v9.5a", "HasV9_5aOps", "true",
"Support ARM v9.5a instructions",
[HasV9_4aOps]>;

// Armv9.6-A is a v9-only architecture.
def HasV9_6aOps : SubtargetFeature<"v9.6a", "HasV9_6aOps", "true",
"Support ARM v9.6a instructions",
[HasV9_5aOps]>;

def HasV8_1MMainlineOps : SubtargetFeature<
"v8.1m.main", "HasV8_1MMainlineOps", "true",
"Support ARM v8-1M Mainline instructions",
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1 change: 1 addition & 0 deletions llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
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Expand Up @@ -894,6 +894,7 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
case ARM::ArchKind::ARMV9_3A:
case ARM::ArchKind::ARMV9_4A:
case ARM::ArchKind::ARMV9_5A:
case ARM::ArchKind::ARMV9_6A:
S.setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
S.setAttributeItem(ARM_ISA_use, Allowed, false);
S.setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
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2 changes: 2 additions & 0 deletions llvm/lib/TargetParser/ARMTargetParser.cpp
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Expand Up @@ -87,6 +87,7 @@ unsigned ARM::parseArchVersion(StringRef Arch) {
case ArchKind::ARMV9_3A:
case ArchKind::ARMV9_4A:
case ArchKind::ARMV9_5A:
case ArchKind::ARMV9_6A:
return 9;
case ArchKind::INVALID:
return 0;
Expand Down Expand Up @@ -125,6 +126,7 @@ static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) {
case ARM::ArchKind::ARMV9_3A:
case ARM::ArchKind::ARMV9_4A:
case ARM::ArchKind::ARMV9_5A:
case ARM::ArchKind::ARMV9_6A:
return ARM::ProfileKind::A;
case ARM::ArchKind::ARMV4:
case ARM::ArchKind::ARMV4T:
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1 change: 1 addition & 0 deletions llvm/lib/TargetParser/ARMTargetParserCommon.cpp
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Expand Up @@ -45,6 +45,7 @@ StringRef ARM::getArchSynonym(StringRef Arch) {
.Case("v9.3a", "v9.3-a")
.Case("v9.4a", "v9.4-a")
.Case("v9.5a", "v9.5-a")
.Case("v9.6a", "v9.6-a")
.Case("v8m.base", "v8-m.base")
.Case("v8m.main", "v8-m.main")
.Case("v8.1m.main", "v8.1-m.main")
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2 changes: 2 additions & 0 deletions llvm/lib/TargetParser/Triple.cpp
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Expand Up @@ -867,6 +867,8 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) {
return Triple::ARMSubArch_v9_4a;
case ARM::ArchKind::ARMV9_5A:
return Triple::ARMSubArch_v9_5a;
case ARM::ArchKind::ARMV9_6A:
return Triple::ARMSubArch_v9_6a;
case ARM::ArchKind::ARMV8R:
return Triple::ARMSubArch_v8r;
case ARM::ArchKind::ARMV8MBaseline:
Expand Down
10 changes: 8 additions & 2 deletions llvm/unittests/TargetParser/TargetParserTest.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ const char *ARMArch[] = {
"armv8m.main", "iwmmxt", "iwmmxt2", "xscale", "armv8.1-m.main",
"armv9-a", "armv9", "armv9a", "armv9.1-a", "armv9.1a",
"armv9.2-a", "armv9.2a", "armv9.3-a", "armv9.3a", "armv9.4-a",
"armv9.4a", "armv9.5-a", "armv9.5a",
"armv9.4a", "armv9.5-a", "armv9.5a", "armv9.6a", "armv9.6-a",
};

std::string FormatExtensionFlags(int64_t Flags) {
Expand Down Expand Up @@ -611,6 +611,8 @@ TEST(TargetParserTest, testARMArch) {
ARMBuildAttrs::CPUArch::v9_A));
EXPECT_TRUE(testARMArch("armv9.5-a", "generic", "v9.5a",
ARMBuildAttrs::CPUArch::v9_A));
EXPECT_TRUE(testARMArch("armv9.6-a", "generic", "v9.6a",
ARMBuildAttrs::CPUArch::v9_A));
EXPECT_TRUE(
testARMArch("armv8-r", "generic", "v8r", ARMBuildAttrs::CPUArch::v8_R));
EXPECT_TRUE(testARMArch("armv8-m.base", "generic", "v8m.base",
Expand Down Expand Up @@ -925,6 +927,7 @@ TEST(TargetParserTest, ARMparseArchProfile) {
case ARM::ArchKind::ARMV9_3A:
case ARM::ArchKind::ARMV9_4A:
case ARM::ArchKind::ARMV9_5A:
case ARM::ArchKind::ARMV9_6A:
EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
break;
default:
Expand Down Expand Up @@ -1186,6 +1189,7 @@ TEST(TargetParserTest, testAArch64Arch) {
EXPECT_TRUE(testAArch64Arch("armv9.3-a"));
EXPECT_TRUE(testAArch64Arch("armv9.4-a"));
EXPECT_TRUE(testAArch64Arch("armv9.5-a"));
EXPECT_TRUE(testAArch64Arch("armv9.6-a"));
}

bool testAArch64Extension(StringRef CPUName, StringRef ArchExt) {
Expand Down Expand Up @@ -1434,6 +1438,7 @@ TEST(TargetParserTest, AArch64ArchFeatures) {
EXPECT_EQ(AArch64::ARMV9_3A.ArchFeature, "+v9.3a");
EXPECT_EQ(AArch64::ARMV9_4A.ArchFeature, "+v9.4a");
EXPECT_EQ(AArch64::ARMV9_5A.ArchFeature, "+v9.5a");
EXPECT_EQ(AArch64::ARMV9_6A.ArchFeature, "+v9.6a");
EXPECT_EQ(AArch64::ARMV8R.ArchFeature, "+v8r");
}

Expand Down Expand Up @@ -1463,7 +1468,7 @@ TEST(TargetParserTest, AArch64ArchPartialOrder) {

for (const auto *A :
{&AArch64::ARMV9_1A, &AArch64::ARMV9_2A, &AArch64::ARMV9_3A,
&AArch64::ARMV9_4A, &AArch64::ARMV9_5A})
&AArch64::ARMV9_4A, &AArch64::ARMV9_5A, &AArch64::ARMV9_6A})
EXPECT_TRUE(A->implies(AArch64::ARMV9A));

EXPECT_TRUE(AArch64::ARMV8_1A.implies(AArch64::ARMV8A));
Expand All @@ -1481,6 +1486,7 @@ TEST(TargetParserTest, AArch64ArchPartialOrder) {
EXPECT_TRUE(AArch64::ARMV9_3A.implies(AArch64::ARMV9_2A));
EXPECT_TRUE(AArch64::ARMV9_4A.implies(AArch64::ARMV9_3A));
EXPECT_TRUE(AArch64::ARMV9_5A.implies(AArch64::ARMV9_4A));
EXPECT_TRUE(AArch64::ARMV9_6A.implies(AArch64::ARMV9_5A));

EXPECT_TRUE(AArch64::ARMV9A.implies(AArch64::ARMV8_5A));
EXPECT_TRUE(AArch64::ARMV9_1A.implies(AArch64::ARMV8_6A));
Expand Down
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