[RISCV][GISEL] instruction-select for G_SPLAT_VECTOR

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

@@ -3303,8 +3303,14 @@ bool IRTranslator::translateShuffleVector(const User &U,
   // poison are treated as zeroinitializer here).
   if (U.getOperand(0)->getType()->isScalableTy()) {
     Register Val = getOrCreateVReg(*U.getOperand(0));
-    auto SplatVal = MIRBuilder.buildExtractVectorElementConstant(
-        MRI->getType(Val).getElementType(), Val, 0);
+    // We don't use buildExtractVectorElementConstant because it creates
+    // problems for CSE since the constant gets placed in a different basic
+    // block.
+    unsigned VecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+    auto *IdxCI = ConstantInt::get(U.getContext(), APInt(VecIdxWidth, 0));
+    Register Idx = getOrCreateVReg(*IdxCI);
+    auto SplatVal = MIRBuilder.buildExtractVectorElement(
+        MRI->getType(Val).getElementType(), Val, Idx);
     MIRBuilder.buildSplatVector(getOrCreateVReg(U), SplatVal);
     return true;
   }

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -68,6 +68,9 @@ class RISCVInstructionSelector : public InstructionSelector {
   // Returns true if the instruction was modified.
   void preISelLower(MachineInstr &MI, MachineIRBuilder &MIB);
 
+  // An early selection function that runs before the selectImpl() call.
+  bool earlySelect(MachineInstr &I);
+
   bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB);
 
   // Custom selection methods
@@ -568,6 +571,9 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     return true;
   }
 
+  if (earlySelect(MI))
+    return true;
+
   if (selectImpl(MI, *CoverageInfo))
     return true;
 
@@ -804,6 +810,49 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
   }
 }
 
+bool RISCVInstructionSelector::earlySelect(MachineInstr &MI) {
+  assert(MI.getParent() && "Instruction should be in a basic block!");
+  assert(MI.getParent()->getParent() && "Instruction should be in a function!");
+
+  MachineIRBuilder MIB(MI);
+
+  switch (MI.getOpcode()) {
+  default:
+    break;
+  case TargetOpcode::G_SPLAT_VECTOR: {
+    // Convert integer SPLAT_VECTOR to VMV_V_X_VL and floating-point
+    // SPLAT_VECTOR to VFMV_V_F_VL to reduce isel burden.
+    Register Scalar = MI.getOperand(1).getReg();
+    bool IsGPRSplat = isRegInGprb(Scalar);
+    const LLT sXLen = LLT::scalar(STI.getXLen());
+    assert((!IsGPRSplat ||
+            TypeSize::isKnownGE(MRI->getType(Scalar).getSizeInBits(),
+                                sXLen.getSizeInBits())) &&
+           "Unexpected Scalar register Type or Size");
+
+    // We create a IMPLICIT_DEF and a G_CONSTANT when we encounter a
+    // G_SPLAT_VECTOR. We cannot select the G_CONSTANT until after the MI is
+    // lowered, since renderVLOp needs to see the G_CONSTANT.
+    // FIXME: It would be nice if the InstructionSelector selected these
+    // instructions without needing to call select on them explicitly,
+    // which would allow us to lower G_SPLAT_VECTOR in preISelLower and
+    // rely on select to do the selection instead of early selecting here.
+    unsigned Opc = IsGPRSplat ? RISCV::G_VMV_V_X_VL : RISCV::G_VFMV_V_F_VL;
+    LLT VecTy = MRI->getType(MI.getOperand(0).getReg());
+    auto Passthru = MIB.buildUndef(VecTy);
+    auto VLMax = MIB.buildConstant(sXLen, -1);
+    MRI->setRegBank(Passthru.getReg(0), RBI.getRegBank(RISCV::VRBRegBankID));
+    MRI->setRegBank(VLMax.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID));
+    auto Splat = MIB.buildInstr(Opc, {MI.getOperand(0).getReg()},
+                                {Passthru, Scalar, VLMax});
+    MI.eraseFromParent();
+    if (selectImpl(*Splat, *CoverageInfo))
+      return select(*Passthru) && select(*VLMax);
+  }
+  }
+  return false;
+}
+
 void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
                                             const MachineInstr &MI,
                                             int OpIdx) const {

llvm/lib/Target/RISCV/RISCVInstrGISel.td

@@ -49,6 +49,22 @@ def G_VMSET_VL : RISCVGenericInstruction {
 }
 def : GINodeEquiv<G_VMSET_VL, riscv_vmset_vl>;
 
+// Pseudo equivalent to a RISCVISD::VMV_V_X_VL
+def G_VMV_V_X_VL : RISCVGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src);
+  let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VMV_V_X_VL, riscv_vmv_v_x_vl>;
+
+// Pseudo equivalent to a RISCVISD::VFMV_V_F_VL
+def G_VFMV_V_F_VL : RISCVGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src);
+  let hasSideEffects = false;
+}
+def : GINodeEquiv<G_VFMV_V_F_VL, riscv_vfmv_v_f_vl>;
+
 // Pseudo equivalent to a RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL. There is no
 // record to mark as equivalent to using GINodeEquiv because it gets lowered
 // before instruction selection.