AMDGPU: Use pointer types more consistently

[arsenm]

This was using addrspace 0 and 1 pointers interchangably. This works
out since they happen to use the same size, but consistently query
or use the correct one.

[arsenm]

• AMDGPU: Add instruction flags when lowering ctor/dtor #111652
• AMDGPU: Use pointer types more consistently #111651 👈
• main

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[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

This was using addrspace 0 and 1 pointers interchangably. This works
out since they happen to use the same size, but consistently query
or use the correct one.

---

Full diff: https://github.com/llvm/llvm-project/pull/111651.diff

4 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp (+7-9)
• (modified) llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll (+1-1)
• (modified) llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll (+1-1)
• (modified) llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll (+1-1)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp
index 6e878a97018760..ea11002bb6a5fa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCtorDtorLowering.cpp
@@ -77,12 +77,12 @@ static void createInitOrFiniCalls(Function &F, bool IsCtor) {
   auto *LoopBB = BasicBlock::Create(C, "while.entry", &F);
   auto *ExitBB = BasicBlock::Create(C, "while.end", &F);
   Type *PtrTy = IRB.getPtrTy(AMDGPUAS::GLOBAL_ADDRESS);
+  ArrayType *PtrArrayTy = ArrayType::get(PtrTy, 0);
 
   auto *Begin = M.getOrInsertGlobal(
-      IsCtor ? "__init_array_start" : "__fini_array_start",
-      ArrayType::get(PtrTy, 0), [&]() {
+      IsCtor ? "__init_array_start" : "__fini_array_start", PtrArrayTy, [&]() {
         return new GlobalVariable(
-            M, ArrayType::get(PtrTy, 0),
+            M, PtrArrayTy,
             /*isConstant=*/true, GlobalValue::ExternalLinkage,
             /*Initializer=*/nullptr,
             IsCtor ? "__init_array_start" : "__fini_array_start",
@@ -90,10 +90,9 @@ static void createInitOrFiniCalls(Function &F, bool IsCtor) {
             /*AddressSpace=*/AMDGPUAS::GLOBAL_ADDRESS);
       });
   auto *End = M.getOrInsertGlobal(
-      IsCtor ? "__init_array_end" : "__fini_array_end",
-      ArrayType::get(PtrTy, 0), [&]() {
+      IsCtor ? "__init_array_end" : "__fini_array_end", PtrArrayTy, [&]() {
         return new GlobalVariable(
-            M, ArrayType::get(PtrTy, 0),
+            M, PtrArrayTy,
             /*isConstant=*/true, GlobalValue::ExternalLinkage,
             /*Initializer=*/nullptr,
             IsCtor ? "__init_array_end" : "__fini_array_end",
@@ -117,7 +116,7 @@ static void createInitOrFiniCalls(Function &F, bool IsCtor) {
     auto *Size = IRB.CreateAShr(ByteSize, ConstantInt::get(Int64Ty, 3));
     auto *Offset = IRB.CreateSub(Size, ConstantInt::get(Int64Ty, 1));
     Start = IRB.CreateInBoundsGEP(
-        ArrayType::get(IRB.getPtrTy(), 0), Begin,
+        PtrArrayTy, Begin,
         ArrayRef<Value *>({ConstantInt::get(Int64Ty, 0), Offset}));
     Stop = Begin;
   }
@@ -128,8 +127,7 @@ static void createInitOrFiniCalls(Function &F, bool IsCtor) {
       LoopBB, ExitBB);
   IRB.SetInsertPoint(LoopBB);
   auto *CallBackPHI = IRB.CreatePHI(PtrTy, 2, "ptr");
-  auto *CallBack = IRB.CreateLoad(IRB.getPtrTy(F.getAddressSpace()),
-                                  CallBackPHI, "callback");
+  auto *CallBack = IRB.CreateLoad(F.getType(), CallBackPHI, "callback");
   IRB.CreateCall(CallBackTy, CallBack);
   auto *NewCallBack =
       IRB.CreateConstGEP1_64(PtrTy, CallBackPHI, IsCtor ? 1 : -1, "next");
diff --git a/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll b/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
index 2ad40ef5e54767..a87e07cb57e05e 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
@@ -66,7 +66,7 @@ define void @bar() addrspace(1) {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = ashr i64 sub (i64 ptrtoint (ptr addrspace(1) @__fini_array_end to i64), i64 ptrtoint (ptr addrspace(1) @__fini_array_start to i64)), 3
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 [[TMP0]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [0 x ptr], ptr addrspace(1) @__fini_array_start, i64 0, i64 [[TMP1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [0 x ptr addrspace(1)], ptr addrspace(1) @__fini_array_start, i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp uge ptr addrspace(1) [[TMP2]], @__fini_array_start
 ; CHECK-NEXT:    br i1 [[TMP3]], label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
 ; CHECK:       while.entry:
diff --git a/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll b/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
index 503f3b1d896f91..a423b320db559d 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
@@ -81,7 +81,7 @@ define internal void @bar() {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = ashr i64 sub (i64 ptrtoint (ptr addrspace(1) @__fini_array_end to i64), i64 ptrtoint (ptr addrspace(1) @__fini_array_start to i64)), 3
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 [[TMP0]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [0 x ptr], ptr addrspace(1) @__fini_array_start, i64 0, i64 [[TMP1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [0 x ptr addrspace(1)], ptr addrspace(1) @__fini_array_start, i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp uge ptr addrspace(1) [[TMP2]], @__fini_array_start
 ; CHECK-NEXT:    br i1 [[TMP3]], label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
 ; CHECK:       while.entry:
diff --git a/llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll b/llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
index 9d00b676d66104..309ecb17e79ed1 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
@@ -73,7 +73,7 @@ define internal void @bar.5() {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = ashr i64 sub (i64 ptrtoint (ptr addrspace(1) @__fini_array_end to i64), i64 ptrtoint (ptr addrspace(1) @__fini_array_start to i64)), 3
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 [[TMP0]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [0 x ptr], ptr addrspace(1) @__fini_array_start, i64 0, i64 [[TMP1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [0 x ptr addrspace(1)], ptr addrspace(1) @__fini_array_start, i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp uge ptr addrspace(1) [[TMP2]], @__fini_array_start
 ; CHECK-NEXT:    br i1 [[TMP3]], label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
 ; CHECK:       while.entry:

[arsenm]

Merge activity

• Oct 9, 9:22 AM EDT: A user started a stack merge that includes this pull request via Graphite.
• Oct 9, 9:23 AM EDT: A user merged this pull request with Graphite.