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[PowerPC] Add custom lowering for ssubo #111748

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Merged
merged 1 commit into from
Oct 29, 2024
Merged

[PowerPC] Add custom lowering for ssubo #111748

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37 changes: 37 additions & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -200,6 +200,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,

setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom);

// On P10, the default lowering generates better code using the
// setbc instruction.
if (!Subtarget.hasP10Vector() && isPPC64)
setOperationAction(ISD::SSUBO, MVT::i32, Custom);

// Match BITREVERSE to customized fast code sequence in the td file.
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
Expand Down Expand Up @@ -12016,6 +12021,36 @@ SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const {
return Res;
}

SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const {

SDLoc dl(Op);

SDValue LHS64 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Op.getOperand(0));
SDValue RHS64 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Op.getOperand(1));

SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i64, LHS64, RHS64);

SDValue Extsw = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i64, Sub,
DAG.getValueType(MVT::i32));

SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i64, Extsw, Sub);

SDValue Addic = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(MVT::i64, MVT::Glue),
Xor, DAG.getConstant(-1, dl, MVT::i64));

SDValue Overflow =
DAG.getNode(ISD::SUBE, dl, DAG.getVTList(MVT::i64, MVT::Glue), Xor, Addic,
Addic.getValue(1));

SDValue OverflowTrunc =
DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow);
SDValue SubTrunc =
(Sub->getValueType(0) != Op.getNode()->getValueType(0))
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Nit: Can probably pull out Op.getNode()->getValueType(0).

? DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(0), Sub)
: Sub;
return DAG.getMergeValues({SubTrunc, OverflowTrunc}, dl);
}

/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Expand All @@ -12038,6 +12073,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SETCC: return LowerSETCC(Op, DAG);
case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
case ISD::SSUBO:
return LowerSSUBO(Op, DAG);
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nit: should we just follow the same fmt as the other lines? I realize it's not clang-format approved...

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It is how clang format modified it. (tried it again)


case ISD::INLINEASM:
case ISD::INLINEASM_BR: return LowerINLINEASM(Op, DAG);
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
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Expand Up @@ -1279,6 +1279,7 @@ namespace llvm {
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUaddo(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
Expand Down
11 changes: 5 additions & 6 deletions llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
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Expand Up @@ -129,12 +129,11 @@ entry:
define i1 @test_ssubo_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_ssubo_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: cmpwi 1, 4, 0
; CHECK-NEXT: cmpw 5, 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: creqv 20, 5, 0
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: sub 3, 3, 4
; CHECK-NEXT: extsw 4, 3
; CHECK-NEXT: xor 3, 4, 3
; CHECK-NEXT: addic 4, 3, -1
; CHECK-NEXT: subfe 3, 4, 3
; CHECK-NEXT: blr
entry:
%res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind
Expand Down
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