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[RISCV] Add missing assembler test case for c.addi zero, 0. NFC #112291

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Oct 15, 2024
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[RISCV] Add missing assembler test case for c.addi zero, 0. NFC #112291

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5 changes: 5 additions & 0 deletions llvm/test/MC/RISCV/rv32c-valid.s
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Original file line number Diff line number Diff line change
Expand Up @@ -147,6 +147,11 @@ c.sub a4, a5
# CHECK-ASM: encoding: [0x01,0x00]
# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.nop
# CHECK-ASM: c.addi zero, 0
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The spec says "C.ADDI is only valid when rd≠x0 and imm≠0".

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@topperc topperc Oct 15, 2024 •
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I know, but this syntax is supported by binutils. We have internal tests from our hardware validation team that uses this syntax.

The isa-manual used to say "C.NOP is encoded as c.addi x0, 0 and so expands to addi x0, x0, 0. Breakpoint Instruction." but it was changed 6 years ago. riscv/riscv-isa-manual#248

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I know, but this syntax is supported by binutils.

Make sense to me.

# CHECK-OBJ: c.nop
# CHECK-ASM: encoding: [0x01,0x00]
# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.addi x0, 0
# CHECK-ASM-AND-OBJ: c.ebreak
# CHECK-ASM: encoding: [0x02,0x90]
# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
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