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Oct 16, 2024
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LVer: improve a test, regen with UTC (NFC) #112544

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140 changes: 107 additions & 33 deletions llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
; RUN: opt -passes=loop-versioning -S < %s | FileCheck %s -check-prefix=LV
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=loop-versioning -S < %s | FileCheck %s

; NB: addrspaces 10-13 are non-integral
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13"
Expand All @@ -12,40 +13,113 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13"

declare i64 @julia_steprange_last_4949()

define void @"japi1_align!_9477"(ptr %arg) {
; LV-LAVEL: L26.lver.check
; LV: [[OFMul:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[Step:%[^ ]*]])
; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 0
; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 1
; LV: [[OFNegMulResult:%[^ ]*]] = sub i64 0, [[OFMulResult]]
; LV-NEXT: [[NegGEP:%[^ ]*]] = getelementptr i8, ptr addrspace(13) [[Base:%[^ ]*]], i64 [[OFNegMulResult]]
; LV-NEXT: icmp ugt ptr addrspace(13) [[NegGEP]], [[Base]]
; LV-NOT: inttoptr
; LV-NOT: ptrtoint
define void @wrapping_ptr_nonint_addrspace(ptr %arg) {
; CHECK-LABEL: define void @wrapping_ptr_nonint_addrspace(
; CHECK-SAME: ptr [[ARG:%.*]]) {
; CHECK-NEXT: [[LOOP_LVER_CHECK:.*:]]
; CHECK-NEXT: [[LOAD0:%.*]] = load ptr addrspace(10), ptr [[ARG]], align 8
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, ptr inttoptr (i64 12 to ptr), align 4
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[LOAD1]]
; CHECK-NEXT: [[CALL:%.*]] = call i64 @julia_steprange_last_4949()
; CHECK-NEXT: [[CAST0:%.*]] = addrspacecast ptr addrspace(10) [[LOAD0]] to ptr addrspace(11)
; CHECK-NEXT: [[LOAD2:%.*]] = load ptr addrspace(10), ptr addrspace(11) [[CAST0]], align 8
; CHECK-NEXT: [[CAST1:%.*]] = addrspacecast ptr addrspace(10) [[LOAD2]] to ptr addrspace(11)
; CHECK-NEXT: [[LOAD3:%.*]] = load ptr addrspace(13), ptr addrspace(11) [[CAST1]], align 8
; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[SUB]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[CALL]], 2
; CHECK-NEXT: [[TMP1:%.*]] = shl nsw i64 [[SEXT]], 2
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], -4
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(13) [[LOAD3]], i64 [[TMP3]]
; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(13) [[LOAD3]], i64 [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP0]], -4
; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr addrspace(13) [[LOAD3]], i64 [[TMP4]]
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr addrspace(13) [[SCEVGEP]], [[LOAD3]]
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr addrspace(13) [[SCEVGEP2]], [[SCEVGEP1]]
; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 0, [[CALL]]
; CHECK-NEXT: [[TMP6:%.*]] = shl nsw i64 [[SEXT]], 2
; CHECK-NEXT: [[TMP7:%.*]] = add nsw i64 [[TMP6]], -4
; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr addrspace(13) [[LOAD3]], i64 [[TMP7]]
; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP5]])
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1
; CHECK-NEXT: [[TMP8:%.*]] = sub i64 0, [[MUL_RESULT]]
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr addrspace(13) [[SCEVGEP3]], i64 [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt ptr addrspace(13) [[TMP9]], [[SCEVGEP3]]
; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP10]], [[MUL_OVERFLOW]]
; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr addrspace(13) [[LOAD3]], i64 -4
; CHECK-NEXT: [[MUL5:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[TMP5]])
; CHECK-NEXT: [[MUL_RESULT6:%.*]] = extractvalue { i64, i1 } [[MUL5]], 0
; CHECK-NEXT: [[MUL_OVERFLOW7:%.*]] = extractvalue { i64, i1 } [[MUL5]], 1
; CHECK-NEXT: [[TMP12:%.*]] = sub i64 0, [[MUL_RESULT6]]
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(13) [[SCEVGEP4]], i64 [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = icmp ugt ptr addrspace(13) [[TMP13]], [[SCEVGEP4]]
; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP14]], [[MUL_OVERFLOW7]]
; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP11]], [[TMP15]]
; CHECK-NEXT: [[LVER_SAFE:%.*]] = or i1 [[FOUND_CONFLICT]], [[TMP16]]
; CHECK-NEXT: br i1 [[LVER_SAFE]], label %[[LOOP_PH_LVER_ORIG:.*]], label %[[LOOP_PH:.*]]
; CHECK: [[LOOP_PH_LVER_ORIG]]:
; CHECK-NEXT: br label %[[LOOP_LVER_ORIG:.*]]
; CHECK: [[LOOP_LVER_ORIG]]:
; CHECK-NEXT: [[VALUE_PHI3_LVER_ORIG:%.*]] = phi i64 [ 0, %[[LOOP_PH_LVER_ORIG]] ], [ [[ADD0_LVER_ORIG:%.*]], %[[LOOP_LVER_ORIG]] ]
; CHECK-NEXT: [[ADD0_LVER_ORIG]] = add i64 [[VALUE_PHI3_LVER_ORIG]], -1
; CHECK-NEXT: [[GEP0_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr addrspace(13) [[LOAD3]], i64 [[ADD0_LVER_ORIG]]
; CHECK-NEXT: [[LOAD4_LVER_ORIG:%.*]] = load i32, ptr addrspace(13) [[GEP0_LVER_ORIG]], align 4
; CHECK-NEXT: [[ADD1_LVER_ORIG:%.*]] = add i64 [[ADD0_LVER_ORIG]], [[SEXT]]
; CHECK-NEXT: [[GEP1_LVER_ORIG:%.*]] = getelementptr inbounds i32, ptr addrspace(13) [[LOAD3]], i64 [[ADD1_LVER_ORIG]]
; CHECK-NEXT: store i32 [[LOAD4_LVER_ORIG]], ptr addrspace(13) [[GEP1_LVER_ORIG]], align 4
; CHECK-NEXT: [[CMP_LVER_ORIG:%.*]] = icmp eq i64 [[VALUE_PHI3_LVER_ORIG]], [[CALL]]
; CHECK-NEXT: br i1 [[CMP_LVER_ORIG]], label %[[EXIT_LOOPEXIT:.*]], label %[[LOOP_LVER_ORIG]]
; CHECK: [[LOOP_PH]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[VALUE_PHI3:%.*]] = phi i64 [ 0, %[[LOOP_PH]] ], [ [[ADD0:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[ADD0]] = add i64 [[VALUE_PHI3]], -1
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr addrspace(13) [[LOAD3]], i64 [[ADD0]]
; CHECK-NEXT: [[LOAD4:%.*]] = load i32, ptr addrspace(13) [[GEP0]], align 4, !alias.scope [[META0:![0-9]+]]
; CHECK-NEXT: [[ADD1:%.*]] = add i64 [[ADD0]], [[SEXT]]
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(13) [[LOAD3]], i64 [[ADD1]]
; CHECK-NEXT: store i32 [[LOAD4]], ptr addrspace(13) [[GEP1]], align 4, !alias.scope [[META3:![0-9]+]], !noalias [[META0]]
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[VALUE_PHI3]], [[CALL]]
; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT_LOOPEXIT8:.*]], label %[[LOOP]]
; CHECK: [[EXIT_LOOPEXIT]]:
; CHECK-NEXT: br label %[[EXIT:.*]]
; CHECK: [[EXIT_LOOPEXIT8]]:
; CHECK-NEXT: br label %[[EXIT]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
top:
%tmp = load ptr addrspace(10), ptr %arg, align 8
%tmp1 = load i32, ptr inttoptr (i64 12 to ptr), align 4
%tmp2 = sub i32 0, %tmp1
%tmp3 = call i64 @julia_steprange_last_4949()
%tmp4 = addrspacecast ptr addrspace(10) %tmp to ptr addrspace(11)
%tmp6 = load ptr addrspace(10), ptr addrspace(11) %tmp4, align 8
%tmp7 = addrspacecast ptr addrspace(10) %tmp6 to ptr addrspace(11)
%tmp9 = load ptr addrspace(13), ptr addrspace(11) %tmp7, align 8
%tmp10 = sext i32 %tmp2 to i64
br label %L26
%load0 = load ptr addrspace(10), ptr %arg, align 8
%load1 = load i32, ptr inttoptr (i64 12 to ptr), align 4
%sub = sub i32 0, %load1
%call = call i64 @julia_steprange_last_4949()
%cast0 = addrspacecast ptr addrspace(10) %load0 to ptr addrspace(11)
%load2 = load ptr addrspace(10), ptr addrspace(11) %cast0, align 8
%cast1 = addrspacecast ptr addrspace(10) %load2 to ptr addrspace(11)
%load3 = load ptr addrspace(13), ptr addrspace(11) %cast1, align 8
%sext = sext i32 %sub to i64
br label %loop

L26:
%value_phi3 = phi i64 [ 0, %top ], [ %tmp11, %L26 ]
%tmp11 = add i64 %value_phi3, -1
%tmp12 = getelementptr inbounds i32, ptr addrspace(13) %tmp9, i64 %tmp11
%tmp13 = load i32, ptr addrspace(13) %tmp12, align 4
%tmp14 = add i64 %tmp11, %tmp10
%tmp15 = getelementptr inbounds i32, ptr addrspace(13) %tmp9, i64 %tmp14
store i32 %tmp13, ptr addrspace(13) %tmp15, align 4
%tmp16 = icmp eq i64 %value_phi3, %tmp3
br i1 %tmp16, label %L45, label %L26
loop:
%value_phi3 = phi i64 [ 0, %top ], [ %add0, %loop ]
%add0 = add i64 %value_phi3, -1
%gep0 = getelementptr inbounds i32, ptr addrspace(13) %load3, i64 %add0
%load4 = load i32, ptr addrspace(13) %gep0, align 4
%add1 = add i64 %add0, %sext
%gep1 = getelementptr inbounds i32, ptr addrspace(13) %load3, i64 %add1
store i32 %load4, ptr addrspace(13) %gep1, align 4
%cmp = icmp eq i64 %value_phi3, %call
br i1 %cmp, label %exit, label %loop

L45:
exit:
ret void
}

;.
; CHECK: [[META0]] = !{[[META1:![0-9]+]]}
; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}
; CHECK: [[META2]] = distinct !{[[META2]], !"LVerDomain"}
; CHECK: [[META3]] = !{[[META4:![0-9]+]]}
; CHECK: [[META4]] = distinct !{[[META4]], [[META2]]}
;.
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