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[DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero #112588

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Nov 5, 2024
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[DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero #112588

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10 changes: 10 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -797,6 +797,16 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
return Op.getOperand(1);
break;
}
case ISD::ADD: {
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Should this also cover or and sub?

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OR is already handled more generally - I'll see if I can get (SUB X, 0) to match in any tests

RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
if (RHSKnown.isZero())
return Op.getOperand(0);

LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
if (LHSKnown.isZero())
return Op.getOperand(1);
break;
}
case ISD::SHL: {
// If we are only demanding sign bits then we can use the shift source
// directly.
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15 changes: 6 additions & 9 deletions llvm/test/CodeGen/AArch64/srem-lkk.ll
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Expand Up @@ -23,12 +23,11 @@ define i32 @fold_srem_positive_even(i32 %x) {
; CHECK-LABEL: fold_srem_positive_even:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #36849 // =0x8ff1
; CHECK-NEXT: mov w9, #1060 // =0x424
; CHECK-NEXT: movk w8, #15827, lsl #16
; CHECK-NEXT: smull x8, w0, w8
; CHECK-NEXT: lsr x9, x8, #63
; CHECK-NEXT: asr x8, x8, #40
; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: mov w9, #1060 // =0x424
; CHECK-NEXT: add w8, w8, w8, lsr #31
; CHECK-NEXT: msub w0, w8, w9, w0
; CHECK-NEXT: ret
%1 = srem i32 %x, 1060
Expand All @@ -40,12 +39,11 @@ define i32 @fold_srem_negative_odd(i32 %x) {
; CHECK-LABEL: fold_srem_negative_odd:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #65445 // =0xffa5
; CHECK-NEXT: mov w9, #-723 // =0xfffffd2d
; CHECK-NEXT: movk w8, #42330, lsl #16
; CHECK-NEXT: smull x8, w0, w8
; CHECK-NEXT: lsr x9, x8, #63
; CHECK-NEXT: asr x8, x8, #40
; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: mov w9, #-723 // =0xfffffd2d
; CHECK-NEXT: add w8, w8, w8, lsr #31
; CHECK-NEXT: msub w0, w8, w9, w0
; CHECK-NEXT: ret
%1 = srem i32 %x, -723
Expand All @@ -57,12 +55,11 @@ define i32 @fold_srem_negative_even(i32 %x) {
; CHECK-LABEL: fold_srem_negative_even:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #62439 // =0xf3e7
; CHECK-NEXT: mov w9, #-22981 // =0xffffa63b
; CHECK-NEXT: movk w8, #64805, lsl #16
; CHECK-NEXT: smull x8, w0, w8
; CHECK-NEXT: lsr x9, x8, #63
; CHECK-NEXT: asr x8, x8, #40
; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: mov w9, #-22981 // =0xffffa63b
; CHECK-NEXT: add w8, w8, w8, lsr #31
; CHECK-NEXT: msub w0, w8, w9, w0
; CHECK-NEXT: ret
%1 = srem i32 %x, -22981
Expand Down
8 changes: 3 additions & 5 deletions llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
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Expand Up @@ -263,16 +263,14 @@ define <2 x i32> @fold_srem_v2i32(<2 x i32> %x) {
; CHECK-LABEL: fold_srem_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #26215 // =0x6667
; CHECK-NEXT: movi v3.2s, #10
; CHECK-NEXT: movi v2.2s, #10
; CHECK-NEXT: movk w8, #26214, lsl #16
; CHECK-NEXT: dup v1.2s, w8
; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: ushr v2.2d, v1.2d, #63
; CHECK-NEXT: sshr v1.2d, v1.2d, #34
; CHECK-NEXT: xtn v2.2s, v2.2d
; CHECK-NEXT: xtn v1.2s, v1.2d
; CHECK-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-NEXT: mls v0.2s, v1.2s, v3.2s
; CHECK-NEXT: usra v1.2s, v1.2s, #31
; CHECK-NEXT: mls v0.2s, v1.2s, v2.2s
; CHECK-NEXT: ret
%1 = srem <2 x i32> %x, <i32 10, i32 10>
ret <2 x i32> %1
Expand Down
38 changes: 14 additions & 24 deletions llvm/test/CodeGen/PowerPC/ppc-32bit-build-vector.ll
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Expand Up @@ -11,45 +11,35 @@ define dso_local fastcc void @BuildVectorICE() unnamed_addr {
; 32BIT-NEXT: stwu 1, -48(1)
; 32BIT-NEXT: .cfi_def_cfa_offset 48
; 32BIT-NEXT: lxvw4x 34, 0, 3
; 32BIT-NEXT: li 3, .LCPI0_0@l
; 32BIT-NEXT: lis 4, .LCPI0_0@ha
; 32BIT-NEXT: li 5, 0
; 32BIT-NEXT: xxlxor 36, 36, 36
; 32BIT-NEXT: lxvw4x 35, 4, 3
; 32BIT-NEXT: addi 3, 1, 16
; 32BIT-NEXT: addi 4, 1, 32
; 32BIT-NEXT: .p2align 4
; 32BIT-NEXT: xxspltw 35, 34, 1
; 32BIT-NEXT: .p2align 5
; 32BIT-NEXT: .LBB0_1: # %while.body
; 32BIT-NEXT: #
; 32BIT-NEXT: stw 5, 16(1)
; 32BIT-NEXT: lxvw4x 37, 0, 3
; 32BIT-NEXT: vperm 5, 5, 4, 3
; 32BIT-NEXT: vadduwm 5, 2, 5
; 32BIT-NEXT: xxspltw 32, 37, 1
; 32BIT-NEXT: vadduwm 5, 5, 0
; 32BIT-NEXT: stxvw4x 37, 0, 4
; 32BIT-NEXT: lxvw4x 36, 0, 3
; 32BIT-NEXT: vadduwm 4, 2, 4
; 32BIT-NEXT: vadduwm 4, 4, 3
; 32BIT-NEXT: stxvw4x 36, 0, 4
; 32BIT-NEXT: lwz 5, 32(1)
; 32BIT-NEXT: b .LBB0_1
;
; 64BIT-LABEL: BuildVectorICE:
; 64BIT: # %bb.0: # %entry
; 64BIT-NEXT: lxvw4x 34, 0, 3
; 64BIT-NEXT: li 3, 0
; 64BIT-NEXT: rldimi 3, 3, 32, 0
; 64BIT-NEXT: mtfprd 0, 3
; 64BIT-NEXT: li 3, 0
; 64BIT-NEXT: .p2align 4
; 64BIT-NEXT: xxspltw 35, 34, 1
; 64BIT-NEXT: .p2align 5
; 64BIT-NEXT: .LBB0_1: # %while.body
; 64BIT-NEXT: #
; 64BIT-NEXT: li 4, 0
; 64BIT-NEXT: rldimi 4, 3, 32, 0
; 64BIT-NEXT: mtfprd 1, 4
; 64BIT-NEXT: xxmrghd 35, 1, 0
; 64BIT-NEXT: vadduwm 3, 2, 3
; 64BIT-NEXT: xxspltw 36, 35, 1
; 64BIT-NEXT: vadduwm 3, 3, 4
; 64BIT-NEXT: xxsldwi 1, 35, 35, 3
; 64BIT-NEXT: mffprwz 3, 1
; 64BIT-NEXT: sldi 3, 3, 32
; 64BIT-NEXT: mtvsrd 36, 3
; 64BIT-NEXT: vadduwm 4, 2, 4
; 64BIT-NEXT: vadduwm 4, 4, 3
; 64BIT-NEXT: xxsldwi 0, 36, 36, 3
; 64BIT-NEXT: mffprwz 3, 0
; 64BIT-NEXT: b .LBB0_1
entry:
br label %while.body
Expand Down
37 changes: 18 additions & 19 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
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Expand Up @@ -13487,7 +13487,6 @@ define <32 x i64> @mgather_strided_split(ptr %base) {
; RV32ZVE32F-NEXT: vid.v v8
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 4
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: lw a3, 0(a1)
; RV32ZVE32F-NEXT: sw a3, 252(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: lw a1, 4(a1)
Expand Down Expand Up @@ -13587,10 +13586,10 @@ define <32 x i64> @mgather_strided_split(ptr %base) {
; RV32ZVE32F-NEXT: lw s9, 4(a1)
; RV32ZVE32F-NEXT: lw s10, 0(a2)
; RV32ZVE32F-NEXT: lw s11, 4(a2)
; RV32ZVE32F-NEXT: lw t5, 0(a3)
; RV32ZVE32F-NEXT: lw t6, 4(a3)
; RV32ZVE32F-NEXT: lw s2, 0(a4)
; RV32ZVE32F-NEXT: lw s3, 4(a4)
; RV32ZVE32F-NEXT: lw s4, 0(a3)
; RV32ZVE32F-NEXT: lw s5, 4(a3)
; RV32ZVE32F-NEXT: lw s6, 0(a4)
; RV32ZVE32F-NEXT: lw s7, 4(a4)
; RV32ZVE32F-NEXT: lw a2, 336(sp)
; RV32ZVE32F-NEXT: lw a4, 340(sp)
; RV32ZVE32F-NEXT: lw a5, 344(sp)
Expand All @@ -13607,8 +13606,8 @@ define <32 x i64> @mgather_strided_split(ptr %base) {
; RV32ZVE32F-NEXT: lw a6, 356(sp)
; RV32ZVE32F-NEXT: lw t3, 360(sp)
; RV32ZVE32F-NEXT: lw t4, 364(sp)
; RV32ZVE32F-NEXT: lw s4, 0(a5)
; RV32ZVE32F-NEXT: sw s4, 116(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: lw t5, 0(a5)
; RV32ZVE32F-NEXT: sw t5, 116(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: lw a5, 4(a5)
; RV32ZVE32F-NEXT: sw a5, 112(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: lw a5, 0(a6)
Expand All @@ -13626,10 +13625,10 @@ define <32 x i64> @mgather_strided_split(ptr %base) {
; RV32ZVE32F-NEXT: lw a6, 372(sp)
; RV32ZVE32F-NEXT: lw t3, 376(sp)
; RV32ZVE32F-NEXT: lw t4, 380(sp)
; RV32ZVE32F-NEXT: lw s4, 0(a5)
; RV32ZVE32F-NEXT: lw s5, 4(a5)
; RV32ZVE32F-NEXT: lw s6, 0(a6)
; RV32ZVE32F-NEXT: lw s7, 4(a6)
; RV32ZVE32F-NEXT: lw t5, 0(a5)
; RV32ZVE32F-NEXT: lw t6, 4(a5)
; RV32ZVE32F-NEXT: lw s2, 0(a6)
; RV32ZVE32F-NEXT: lw s3, 4(a6)
; RV32ZVE32F-NEXT: lw a5, 0(t3)
; RV32ZVE32F-NEXT: lw a6, 4(t3)
; RV32ZVE32F-NEXT: lw t3, 0(t4)
Expand All @@ -13642,10 +13641,10 @@ define <32 x i64> @mgather_strided_split(ptr %base) {
; RV32ZVE32F-NEXT: sw t0, 164(a0)
; RV32ZVE32F-NEXT: sw t1, 168(a0)
; RV32ZVE32F-NEXT: sw t2, 172(a0)
; RV32ZVE32F-NEXT: sw t5, 144(a0)
; RV32ZVE32F-NEXT: sw t6, 148(a0)
; RV32ZVE32F-NEXT: sw s2, 152(a0)
; RV32ZVE32F-NEXT: sw s3, 156(a0)
; RV32ZVE32F-NEXT: sw s4, 144(a0)
; RV32ZVE32F-NEXT: sw s5, 148(a0)
; RV32ZVE32F-NEXT: sw s6, 152(a0)
; RV32ZVE32F-NEXT: sw s7, 156(a0)
; RV32ZVE32F-NEXT: sw s8, 128(a0)
; RV32ZVE32F-NEXT: sw s9, 132(a0)
; RV32ZVE32F-NEXT: sw s10, 136(a0)
Expand Down Expand Up @@ -13686,10 +13685,10 @@ define <32 x i64> @mgather_strided_split(ptr %base) {
; RV32ZVE32F-NEXT: sw a6, 244(a0)
; RV32ZVE32F-NEXT: sw t3, 248(a0)
; RV32ZVE32F-NEXT: sw t4, 252(a0)
; RV32ZVE32F-NEXT: sw s4, 224(a0)
; RV32ZVE32F-NEXT: sw s5, 228(a0)
; RV32ZVE32F-NEXT: sw s6, 232(a0)
; RV32ZVE32F-NEXT: sw s7, 236(a0)
; RV32ZVE32F-NEXT: sw t5, 224(a0)
; RV32ZVE32F-NEXT: sw t6, 228(a0)
; RV32ZVE32F-NEXT: sw s2, 232(a0)
; RV32ZVE32F-NEXT: sw s3, 236(a0)
; RV32ZVE32F-NEXT: sw ra, 208(a0)
; RV32ZVE32F-NEXT: lw a1, 108(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: sw a1, 212(a0)
Expand Down
45 changes: 19 additions & 26 deletions llvm/test/CodeGen/X86/combine-pmuldq.ll
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Expand Up @@ -203,46 +203,39 @@ define i32 @PR43159(ptr %a0) {
; SSE-LABEL: PR43159:
; SSE: # %bb.0: # %entry
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrld $1, %xmm1
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; SSE-NEXT: psubd %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: psrld $1, %xmm2
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1,2,3],xmm2[4,5],xmm0[6,7]
; SSE-NEXT: psubd %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
; SSE-NEXT: paddd %xmm1, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: psrld $7, %xmm0
; SSE-NEXT: psrld $6, %xmm2
; SSE-NEXT: movd %xmm2, %edi
; SSE-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: psrld $6, %xmm1
; SSE-NEXT: movd %xmm1, %edi
; SSE-NEXT: pextrd $1, %xmm0, %esi
; SSE-NEXT: pextrd $2, %xmm2, %edx
; SSE-NEXT: pextrd $2, %xmm1, %edx
; SSE-NEXT: pextrd $3, %xmm0, %ecx
; SSE-NEXT: jmp foo # TAILCALL
;
; AVX1-LABEL: PR43159:
; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; AVX1-NEXT: vpsubd %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; AVX1-NEXT: vpaddd %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpsrld $7, %xmm1, %xmm1
; AVX1-NEXT: vpsrld $1, %xmm0, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5],xmm0[6,7]
; AVX1-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsrld $7, %xmm0, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; AVX1-NEXT: vpsrld $6, %xmm0, %xmm0
; AVX1-NEXT: vmovd %xmm0, %edi
; AVX1-NEXT: vpextrd $1, %xmm1, %esi
Expand Down
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