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[AMDGPU] Factor out getNumUsedPhysRegs(). NFC. #112624

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Merged
merged 4 commits into from
Oct 17, 2024
Merged

[AMDGPU] Factor out getNumUsedPhysRegs(). NFC. #112624

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166199f
[AMDGPU] Factor out getNumUsedPhysRegs(). NFC.
rampitec Oct 16, 2024
5860c18
Merge branch 'main' into get-num-used-phys-regs
rampitec Oct 16, 2024
25aed86
Fix the merge
rampitec Oct 16, 2024
be307be
Fix the merge
rampitec Oct 16, 2024
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42 changes: 4 additions & 38 deletions llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -146,44 +146,10 @@ AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
// count easily.
// A tail call isn't considered a call for MachineFrameInfo's purposes.
if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
if (MRI.isPhysRegUsed(Reg)) {
HighestVGPRReg = Reg;
break;
}
}

if (ST.hasMAIInsts()) {
MCPhysReg HighestAGPRReg = AMDGPU::NoRegister;
for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) {
if (MRI.isPhysRegUsed(Reg)) {
HighestAGPRReg = Reg;
break;
}
}
Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister
? 0
: TRI.getHWRegIndex(HighestAGPRReg) + 1;
}

MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
if (MRI.isPhysRegUsed(Reg)) {
HighestSGPRReg = Reg;
break;
}
}

// We found the maximum register index. They start at 0, so add one to get
// the number of registers.
Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister
? 0
: TRI.getHWRegIndex(HighestVGPRReg) + 1;
Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister
? 0
: TRI.getHWRegIndex(HighestSGPRReg) + 1;

Info.NumVGPR = TRI.getNumUsedPhysRegs(MRI, AMDGPU::VGPR_32RegClass);
Info.NumExplicitSGPR = TRI.getNumUsedPhysRegs(MRI, AMDGPU::SGPR_32RegClass);
if (ST.hasMAIInsts())
Info.NumAGPR = TRI.getNumUsedPhysRegs(MRI, AMDGPU::AGPR_32RegClass);
return Info;
}

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9 changes: 9 additions & 0 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -3851,3 +3851,12 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
}
return 0;
}

unsigned
SIRegisterInfo::getNumUsedPhysRegs(const MachineRegisterInfo &MRI,
const TargetRegisterClass &RC) const {
for (MCPhysReg Reg : reverse(RC.getRegisters()))
if (MRI.isPhysRegUsed(Reg))
return getHWRegIndex(Reg) + 1;
return 0;
}
5 changes: 5 additions & 0 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.h
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Expand Up @@ -457,6 +457,11 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;

// \returns a number of registers of a given \p RC used in a function.
// Does not go inside function calls.
unsigned getNumUsedPhysRegs(const MachineRegisterInfo &MRI,
const TargetRegisterClass &RC) const;
};

namespace AMDGPU {
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