[NFC][AMDGPU] clang-format llvm/lib/Target/AMDGPU/SIISelLowering.cpp
#112645
+861
−852
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@llvm/pr-subscribers-backend-amdgpu Author: Shilei Tian (shiltian) ChangesPatch is 170.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/112645.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index de9173e923ab5c..312f915f8908e9 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -51,16 +51,15 @@ using namespace llvm;
STATISTIC(NumTailCalls, "Number of tail calls");
-static cl::opt<bool> DisableLoopAlignment(
- "amdgpu-disable-loop-alignment",
- cl::desc("Do not align and prefetch loops"),
- cl::init(false));
+static cl::opt<bool>
+ DisableLoopAlignment("amdgpu-disable-loop-alignment",
+ cl::desc("Do not align and prefetch loops"),
+ cl::init(false));
static cl::opt<bool> UseDivergentRegisterIndexing(
- "amdgpu-use-divergent-register-indexing",
- cl::Hidden,
- cl::desc("Use indirect register addressing for divergent indexes"),
- cl::init(false));
+ "amdgpu-use-divergent-register-indexing", cl::Hidden,
+ cl::desc("Use indirect register addressing for divergent indexes"),
+ cl::init(false));
static bool denormalModeIsFlushAllF32(const MachineFunction &MF) {
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
@@ -84,8 +83,7 @@ static unsigned findFirstFreeSGPR(CCState &CCInfo) {
SITargetLowering::SITargetLowering(const TargetMachine &TM,
const GCNSubtarget &STI)
- : AMDGPUTargetLowering(TM, STI),
- Subtarget(&STI) {
+ : AMDGPUTargetLowering(TM, STI), Subtarget(&STI) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
@@ -192,17 +190,17 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
// We need to custom lower vector stores from local memory
setOperationAction(ISD::LOAD,
- {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
- MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
+ {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
+ MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
MVT::v10i32, MVT::v11i32, MVT::v12i32, MVT::v16i32,
- MVT::i1, MVT::v32i32},
+ MVT::i1, MVT::v32i32},
Custom);
setOperationAction(ISD::STORE,
- {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
- MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
+ {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
+ MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
MVT::v10i32, MVT::v11i32, MVT::v12i32, MVT::v16i32,
- MVT::i1, MVT::v32i32},
+ MVT::i1, MVT::v32i32},
Custom);
if (isTypeLegal(MVT::bf16)) {
@@ -278,13 +276,13 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
setOperationAction(ISD::TRUNCATE,
- {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
- MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
+ {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
+ MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
MVT::v10i32, MVT::v11i32, MVT::v12i32, MVT::v16i32},
Expand);
setOperationAction(ISD::FP_ROUND,
- {MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32,
- MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v9f32,
+ {MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32,
+ MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v9f32,
MVT::v10f32, MVT::v11f32, MVT::v12f32, MVT::v16f32},
Expand);
@@ -350,7 +348,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
// Most operations are naturally 32-bit vector operations. We only support
// load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
- for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
+ for (MVT Vec64 : {MVT::v2i64, MVT::v2f64}) {
setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
@@ -364,7 +362,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
}
- for (MVT Vec64 : { MVT::v3i64, MVT::v3f64 }) {
+ for (MVT Vec64 : {MVT::v3i64, MVT::v3f64}) {
setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v6i32);
@@ -378,7 +376,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v6i32);
}
- for (MVT Vec64 : { MVT::v4i64, MVT::v4f64 }) {
+ for (MVT Vec64 : {MVT::v4i64, MVT::v4f64}) {
setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v8i32);
@@ -392,7 +390,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v8i32);
}
- for (MVT Vec64 : { MVT::v8i64, MVT::v8f64 }) {
+ for (MVT Vec64 : {MVT::v8i64, MVT::v8f64}) {
setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v16i32);
@@ -406,7 +404,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32);
}
- for (MVT Vec64 : { MVT::v16i64, MVT::v16f64 }) {
+ for (MVT Vec64 : {MVT::v16i64, MVT::v16f64}) {
setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v32i32);
@@ -440,9 +438,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
// Deal with vec5/6/7 vector operations when widened to vec8.
setOperationAction(ISD::INSERT_SUBVECTOR,
- {MVT::v5i32, MVT::v5f32, MVT::v6i32, MVT::v6f32,
- MVT::v7i32, MVT::v7f32, MVT::v8i32, MVT::v8f32,
- MVT::v9i32, MVT::v9f32, MVT::v10i32, MVT::v10f32,
+ {MVT::v5i32, MVT::v5f32, MVT::v6i32, MVT::v6f32,
+ MVT::v7i32, MVT::v7f32, MVT::v8i32, MVT::v8f32,
+ MVT::v9i32, MVT::v9f32, MVT::v10i32, MVT::v10f32,
MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32},
Custom);
@@ -782,8 +780,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
ISD::FMAXNUM_IEEE, ISD::FCANONICALIZE},
MVT::v2f16, Legal);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, {MVT::v2i16, MVT::v2f16, MVT::v2bf16},
- Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT,
+ {MVT::v2i16, MVT::v2f16, MVT::v2bf16}, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE,
{MVT::v4f16, MVT::v4i16, MVT::v8f16, MVT::v8i16,
@@ -969,9 +967,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setSchedulingPreference(Sched::RegPressure);
}
-const GCNSubtarget *SITargetLowering::getSubtarget() const {
- return Subtarget;
-}
+const GCNSubtarget *SITargetLowering::getSubtarget() const { return Subtarget; }
ArrayRef<MCPhysReg> SITargetLowering::getRoundingControlRegisters() const {
static const MCPhysReg RCRegs[] = {AMDGPU::MODE};
@@ -1068,9 +1064,8 @@ unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
}
unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
- LLVMContext &Context, CallingConv::ID CC,
- EVT VT, EVT &IntermediateVT,
- unsigned &NumIntermediates, MVT &RegisterVT) const {
+ LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
+ unsigned &NumIntermediates, MVT &RegisterVT) const {
if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
unsigned NumElts = VT.getVectorNumElements();
EVT ScalarVT = VT.getScalarType();
@@ -1105,7 +1100,6 @@ unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
return NumIntermediates;
}
-
if (Size != 16 && Size <= 32) {
RegisterVT = MVT::i32;
IntermediateVT = ScalarVT;
@@ -1122,7 +1116,7 @@ unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
}
return TargetLowering::getVectorTypeBreakdownForCallingConv(
- Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
+ Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
}
static EVT memVTFromLoadIntrData(const SITargetLowering &TLI,
@@ -1192,8 +1186,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
AMDGPU::lookupRsrcIntrinsic(IntrID)) {
- AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
- (Intrinsic::ID)IntrID);
+ AttributeList Attr =
+ Intrinsic::getAttributes(CI.getContext(), (Intrinsic::ID)IntrID);
MemoryEffects ME = Attr.getMemoryEffects();
if (ME.doesNotAccessMemory())
return false;
@@ -1235,8 +1229,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
if (!BaseOpcode->Gather4) {
// If this isn't a gather, we may have excess loaded elements in the
// IR type. Check the dmask for the real number of elements loaded.
- unsigned DMask
- = cast<ConstantInt>(CI.getArgOperand(0))->getZExtValue();
+ unsigned DMask =
+ cast<ConstantInt>(CI.getArgOperand(0))->getZExtValue();
MaxNumLanes = DMask == 0 ? 1 : llvm::popcount(DMask);
}
@@ -1266,8 +1260,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
Info.flags |= MachineMemOperand::MOStore;
} else {
// Atomic, NoReturn Sampler or prefetch
- Info.opc = CI.getType()->isVoidTy() ? ISD::INTRINSIC_VOID :
- ISD::INTRINSIC_W_CHAIN;
+ Info.opc = CI.getType()->isVoidTy() ? ISD::INTRINSIC_VOID
+ : ISD::INTRINSIC_W_CHAIN;
Info.flags |=
MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable;
@@ -1352,8 +1346,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
Info.memVT = MVT::getVT(CI.getType());
Info.ptrVal = CI.getOperand(0);
Info.align.reset();
- Info.flags |= MachineMemOperand::MOLoad |
- MachineMemOperand::MOStore |
+ Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore |
MachineMemOperand::MOVolatile;
return true;
}
@@ -1363,8 +1356,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
Info.fallbackAddressSpace = AMDGPUAS::BUFFER_RESOURCE;
Info.align.reset();
- Info.flags |= MachineMemOperand::MOLoad |
- MachineMemOperand::MODereferenceable;
+ Info.flags |=
+ MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable;
return true;
}
case Intrinsic::amdgcn_global_atomic_fmin_num:
@@ -1377,8 +1370,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
Info.memVT = MVT::getVT(CI.getType());
Info.ptrVal = CI.getOperand(0);
Info.align.reset();
- Info.flags |= MachineMemOperand::MOLoad |
- MachineMemOperand::MOStore |
+ Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore |
MachineMemOperand::MODereferenceable |
MachineMemOperand::MOVolatile;
return true;
@@ -1472,7 +1464,7 @@ void SITargetLowering::CollectTargetIntrinsicOperands(
}
bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
- SmallVectorImpl<Value*> &Ops,
+ SmallVectorImpl<Value *> &Ops,
Type *&AccessTy) const {
Value *Ptr = nullptr;
switch (II->getIntrinsicID()) {
@@ -1578,7 +1570,8 @@ bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, Type *Ty,
- unsigned AS, Instruction *I) const {
+ unsigned AS,
+ Instruction *I) const {
// No global is ever allowed as a base.
if (AM.BaseGV)
return false;
@@ -1970,16 +1963,16 @@ SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
return DAG.getConstant(Offset, SL, PtrVT);
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
- SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
- MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
+ SDValue BasePtr = DAG.getCopyFromReg(
+ Chain, SL, MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
return DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::getFixed(Offset));
}
SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
const SDLoc &SL) const {
- uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
- FIRST_IMPLICIT);
+ uint64_t Offset =
+ getImplicitParameterOffset(DAG.getMachineFunction(), FIRST_IMPLICIT);
return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
}
@@ -2009,8 +2002,7 @@ SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
}
// Then convert the vector elements or scalar value.
- if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
- VT.bitsLT(MemVT)) {
+ if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) && VT.bitsLT(MemVT)) {
unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
}
@@ -2055,8 +2047,7 @@ SDValue SITargetLowering::lowerKernargMemParameter(
ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
-
- return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
+ return DAG.getMergeValues({ArgVal, Load.getValue(1)}, SL);
}
SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
@@ -2065,11 +2056,12 @@ SDValue SITargetLowering::lowerKernargMemParameter(
MachineMemOperand::MOInvariant);
SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
- return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
+ return DAG.getMergeValues({Val, Load.getValue(1)}, SL);
}
-SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
- const SDLoc &SL, SDValue Chain,
+SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG,
+ CCValAssign &VA, const SDLoc &SL,
+ SDValue Chain,
const ISD::InputArg &Arg) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -2111,16 +2103,14 @@ SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA
}
ArgValue = DAG.getExtLoad(
- ExtType, SL, VA.getLocVT(), Chain, FIN,
- MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
- MemVT);
+ ExtType, SL, VA.getLocVT(), Chain, FIN,
+ MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), MemVT);
return ArgValue;
}
-SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
- const SIMachineFunctionInfo &MFI,
- EVT VT,
- AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
+SDValue SITargetLowering::getPreloadedValue(
+ SelectionDAG &DAG, const SIMachineFunctionInfo &MFI, EVT VT,
+ AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
const ArgDescriptor *Reg = nullptr;
const TargetRegisterClass *RC;
LLT Ty;
@@ -2189,8 +2179,8 @@ static void processPSInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
"vector type argument should have been split");
// First check if it's a PS input addr.
- if (CallConv == CallingConv::AMDGPU_PS &&
- !Arg->Flags.isInReg() && PSInputNum <= 15) {
+ if (CallConv == CallingConv::AMDGPU_PS && !Arg->Flags.isInReg() &&
+ PSInputNum <= 15) {
bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
// Inconveniently only the first part of the split is marked as isSplit,
@@ -2198,8 +2188,7 @@ static void processPSInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
// entire split argument.
if (Arg->Flags.isSplit()) {
while (!Arg->Flags.isSplitEnd()) {
- assert((!Arg->VT.isVector() ||
- Arg->VT.getScalarSizeInBits() == 16) &&
+ assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&
"unexpected vector split in ps argument type");
if (!SkipArg)
Splits.push_back(*Arg);
@@ -2226,10 +2215,9 @@ static void processPSInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
}
// Allocate special inputs passed in VGPRs.
-void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
- MachineFunction &MF,
- const SIRegisterInfo &TRI,
- SIMachineFunctionInfo &Info) const {
+void SITargetLowering::allocateSpecialEntryInputVGPRs(
+ CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI,
+ SIMachineFunctionInfo &Info) const {
const LLT S32 = LLT::scalar(32);
MachineRegisterInfo &MRI = MF.getRegInfo();
@@ -2238,16 +2226,16 @@ void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
CCInfo.AllocateReg(Reg);
- unsigned Mask = (Subtarget->hasPackedTID() &&
- Info.hasWorkItemIDY()) ? 0x3ff : ~0u;
+ unsigned Mask =
+ (Subtarget->hasPackedTID() && Info.hasWorkItemIDY()) ? 0x3ff : ~0u;
Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask));
}
if (Info.hasWorkItemIDY()) {
assert(Info.hasWorkItemIDX());
if (Subtarget->hasPackedTID()) {
- Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0,
- 0x3ff << 10));
+ Info.setWorkItemIDY(
+ ArgDescriptor::createRegister(AMDGPU::VGPR0, 0x3ff << 10));
} else {
unsigned Reg = AMDGPU::VGPR1;
MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
@@ -2260,8 +2248,8 @@ void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
if (Info.hasWorkItemIDZ()) {
assert(Info.hasWorkItemIDX() && Info.hasWorkItemIDY());
if (Subtarget->hasPackedTID()) {
- Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0,
- 0x3ff << 20));
+ Info.setWorkItemIDZ(
+ ArgDescriptor::createRegister(AMDGPU::VGPR0, 0x3ff << 20));
} else {
unsigned Reg = AMDGPU::VGPR2;
MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
@@ -2348,8 +2336,8 @@ static void allocateSGPR64Input(CCState &CCInfo, ArgDescriptor &Arg) {
/// Allocate implicit function VGPR arguments at the end of allocated user
/// arguments.
void SITargetLowering::allocateSpecialInputVGPRs(
- CCState &CCInfo, MachineFunction &MF,
- const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
+ CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI,
+ SIMachineFunctionInfo &Info) const {
const unsigned Mask = 0x3ff;
ArgDescriptor Arg;
@@ -2369,8 +2357,8 @@ void SITargetLowering::allocateSpecialInputVGPRs(
/// Allocate implicit function VGPR arguments in fixed registers.
void SITargetLowering::allocateSpecialInputVGPRsFixed(
- CCState &CCInfo, MachineFunction &MF,
- const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
+ ...
[truncated]
|
|
This is a pretty intrusive change. I can understand the reason if we don't want to do it, but the format of some code is really off. |
arsenm
reviewed
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Oct 21, 2024
| const TargetRegisterClass *RC = | ||
| getRegForInlineAsmConstraint(SIRI, TC.ConstraintCode, | ||
| TC.ConstraintVT) | ||
| .second; |
There was a problem hiding this comment.
I don't know why clang-format really wants to force things onto one line, and then sometimes produces these ugly breaks
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/7375 Here is the relevant piece of the build log for the reference |
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