Fix typo "instrinsic" #112899

jayfoad · 2024-10-18T12:56:02Z

No description provided.

llvmbot · 2024-10-18T12:56:35Z

@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-mlir
@llvm/pr-subscribers-mlir-llvm
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-lldb
@llvm/pr-subscribers-backend-webassembly

@llvm/pr-subscribers-clang

Author: Jay Foad (jayfoad)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/112899.diff

19 Files Affected:

(modified) clang/utils/TableGen/RISCVVEmitter.cpp (+2-2)
(modified) flang/docs/OptionComparison.md (+1-1)
(modified) flang/include/flang/Runtime/magic-numbers.h (+1-1)
(modified) flang/lib/Evaluate/intrinsics.cpp (+1-1)
(modified) flang/lib/Optimizer/Builder/Runtime/Numeric.cpp (+3-3)
(modified) flang/lib/Optimizer/Builder/Runtime/Reduction.cpp (+1-1)
(modified) lldb/CMakeLists.txt (+1-1)
(modified) llvm/include/llvm/IR/IntrinsicsAMDGPU.td (+1-1)
(modified) llvm/include/llvm/Transforms/Utils/SSAUpdater.h (+1-1)
(modified) llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp (+1-1)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+1-1)
(modified) llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (+1-1)
(modified) llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll (+1-1)
(modified) llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll (+1-1)
(modified) llvm/test/Transforms/JumpThreading/thread-debug-info.ll (+1-1)
(modified) llvm/test/Transforms/SROA/fake-use-sroa.ll (+1-1)
(modified) llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp (+1-1)
(modified) mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp (+1-1)
(modified) mlir/lib/Target/LLVMIR/ModuleImport.cpp (+1-1)

diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index 50f161fd38ce69..aecca0f5df8d93 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -169,7 +169,7 @@ static VectorTypeModifier getTupleVTM(unsigned NF) {
 
 static unsigned getIndexedLoadStorePtrIdx(const RVVIntrinsic *RVVI) {
   // We need a special rule for segment load/store since the data width is not
-  // encoded in the instrinsic name itself.
+  // encoded in the intrinsic name itself.
   const StringRef IRName = RVVI->getIRName();
   constexpr unsigned RVV_VTA = 0x1;
   constexpr unsigned RVV_VMA = 0x2;
@@ -192,7 +192,7 @@ static unsigned getIndexedLoadStorePtrIdx(const RVVIntrinsic *RVVI) {
 static unsigned getSegInstLog2SEW(StringRef InstName) {
   // clang-format off
   // We need a special rule for indexed segment load/store since the data width
-  // is not encoded in the instrinsic name itself.
+  // is not encoded in the intrinsic name itself.
   if (InstName.starts_with("vloxseg") || InstName.starts_with("vluxseg") ||
       InstName.starts_with("vsoxseg") || InstName.starts_with("vsuxseg"))
     return (unsigned)-1;
diff --git a/flang/docs/OptionComparison.md b/flang/docs/OptionComparison.md
index 9d6916ef62af2e..fb65498fa1f444 100644
--- a/flang/docs/OptionComparison.md
+++ b/flang/docs/OptionComparison.md
@@ -53,7 +53,7 @@ eN
    </td>
    <td>fdec,
 <p>
-fall-instrinsics
+fall-intrinsics
    </td>
    <td><a href="https://www-01.ibm.com/support/docview.wss?uid=swg27024803&aid=1#page=297">qxlf77</a>,
 <p>
diff --git a/flang/include/flang/Runtime/magic-numbers.h b/flang/include/flang/Runtime/magic-numbers.h
index bab0e9ae05299a..1d3c5dca0b4bfb 100644
--- a/flang/include/flang/Runtime/magic-numbers.h
+++ b/flang/include/flang/Runtime/magic-numbers.h
@@ -107,7 +107,7 @@ The denorm value is a nonstandard extension.
 
 #if 0
 ieee_round_type values
-The values are those of the llvm.get.rounding instrinsic, which is assumed by
+The values are those of the llvm.get.rounding intrinsic, which is assumed by
 ieee_arithmetic module rounding procedures.
 #endif
 #define _FORTRAN_RUNTIME_IEEE_TO_ZERO 0
diff --git a/flang/lib/Evaluate/intrinsics.cpp b/flang/lib/Evaluate/intrinsics.cpp
index 4271faa0db12bf..aa44967817722e 100644
--- a/flang/lib/Evaluate/intrinsics.cpp
+++ b/flang/lib/Evaluate/intrinsics.cpp
@@ -1690,7 +1690,7 @@ std::optional<SpecificCall> IntrinsicInterface::Match(
   // MAX and MIN (and others that map to them) allow their last argument to
   // be repeated indefinitely.  The actualForDummy vector is sized
   // and null-initialized to the non-repeated dummy argument count
-  // for other instrinsics.
+  // for other intrinsics.
   bool isMaxMin{dummyArgPatterns > 0 &&
       dummy[dummyArgPatterns - 1].optionality == Optionality::repeats};
   std::vector<ActualArgument *> actualForDummy(
diff --git a/flang/lib/Optimizer/Builder/Runtime/Numeric.cpp b/flang/lib/Optimizer/Builder/Runtime/Numeric.cpp
index c13064a284d127..d0092add0118f1 100644
--- a/flang/lib/Optimizer/Builder/Runtime/Numeric.cpp
+++ b/flang/lib/Optimizer/Builder/Runtime/Numeric.cpp
@@ -284,7 +284,7 @@ struct ForcedSpacing16 {
   }
 };
 
-/// Generate call to Exponent instrinsic runtime routine.
+/// Generate call to Exponent intrinsic runtime routine.
 mlir::Value fir::runtime::genExponent(fir::FirOpBuilder &builder,
                                       mlir::Location loc, mlir::Type resultType,
                                       mlir::Value x) {
@@ -320,7 +320,7 @@ mlir::Value fir::runtime::genExponent(fir::FirOpBuilder &builder,
   return builder.create<fir::CallOp>(loc, func, args).getResult(0);
 }
 
-/// Generate call to Fraction instrinsic runtime routine.
+/// Generate call to Fraction intrinsic runtime routine.
 mlir::Value fir::runtime::genFraction(fir::FirOpBuilder &builder,
                                       mlir::Location loc, mlir::Value x) {
   mlir::func::FuncOp func;
@@ -596,7 +596,7 @@ mlir::Value fir::runtime::genSelectedRealKind(fir::FirOpBuilder &builder,
   return builder.create<fir::CallOp>(loc, func, args).getResult(0);
 }
 
-/// Generate call to Set_exponent instrinsic runtime routine.
+/// Generate call to Set_exponent intrinsic runtime routine.
 mlir::Value fir::runtime::genSetExponent(fir::FirOpBuilder &builder,
                                          mlir::Location loc, mlir::Value x,
                                          mlir::Value i) {
diff --git a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
index f6627dff671e6f..b768733bd2fd8f 100644
--- a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
+++ b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
@@ -1513,7 +1513,7 @@ mlir::Value fir::runtime::genSum(fir::FirOpBuilder &builder, mlir::Location loc,
 
 // The IAll, IAny and IParity intrinsics have essentially the same
 // implementation. This macro will generate the function body given the
-// instrinsic name.
+// intrinsic name.
 #define GEN_IALL_IANY_IPARITY(F)                                               \
   mlir::Value fir::runtime::JOIN2(gen, F)(                                     \
       fir::FirOpBuilder & builder, mlir::Location loc, mlir::Value arrayBox,   \
diff --git a/lldb/CMakeLists.txt b/lldb/CMakeLists.txt
index 59cdc4593463c1..5827e04b5662f3 100644
--- a/lldb/CMakeLists.txt
+++ b/lldb/CMakeLists.txt
@@ -97,7 +97,7 @@ if (LLDB_ENABLE_PYTHON OR LLDB_ENABLE_LUA)
   add_subdirectory(bindings)
 endif ()
 
-# We need the headers generated by instrinsics_gen before we can compile
+# We need the headers generated by intrinsics_gen before we can compile
 # any source file in LLDB as the imported Clang modules might include
 # some of these generated headers. This approach is copied from Clang's main
 # CMakeLists.txt, so it should kept in sync the code in Clang which was added
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 715f2cc917e21c..92226a687cad40 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -1115,7 +1115,7 @@ def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic <
 // it is const 0. A struct intrinsic with constant 0 index is different to the
 // corresponding raw intrinsic on gfx9+ because the behavior of bound checking
 // and swizzling changes depending on whether idxen is set in the instruction.
-// These instrinsics also keep the offset and soffset arguments separate as
+// These intrinsics also keep the offset and soffset arguments separate as
 // they behave differently in bounds checking and swizzling.
 
 // The versions of these intrinsics that take <4 x i32> arguments are deprecated
diff --git a/llvm/include/llvm/Transforms/Utils/SSAUpdater.h b/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
index 29d96a0ab6bf5b..73649766a95388 100644
--- a/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
+++ b/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
@@ -118,7 +118,7 @@ class SSAUpdater {
 
   /// Rewrite debug value intrinsics to conform to a new SSA form.
   ///
-  /// This will scout out all the debug value instrinsics associated with
+  /// This will scout out all the debug value intrinsics associated with
   /// the instruction. Anything outside of its block will have its
   /// value set to the new SSA value if available, and undef if not.
   void UpdateDebugValues(Instruction *I);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
index ee5e75955cd459..e4ca1ae0499b93 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
@@ -580,7 +580,7 @@ std::pair<Value *, Value *> AMDGPUAtomicOptimizerImpl::buildScanIteratively(
   auto *ActiveBits = B.CreatePHI(WaveTy, 2, "ActiveBits");
   ActiveBits->addIncoming(Ballot, EntryBB);
 
-  // Use llvm.cttz instrinsic to find the lowest remaining active lane.
+  // Use llvm.cttz intrinsic to find the lowest remaining active lane.
   auto *FF1 =
       B.CreateIntrinsic(Intrinsic::cttz, WaveTy, {ActiveBits, B.getTrue()});
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 68182d238e7847..6b308bc8c9aa0f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -50,7 +50,7 @@
 /// each of the preceding fields which are relevant for a given instruction
 /// in the opcode space.
 ///
-/// Currently, the policy is represented via the following instrinsic families:
+/// Currently, the policy is represented via the following intrinsic families:
 /// * _MASK - Can represent all three policy states for both tail and mask.  If
 ///   passthrough is IMPLICIT_DEF (or NoReg), then represents "undefined".
 ///   Otherwise, policy operand and tablegen flags drive the interpretation.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 60b3294b5f0bd0..2c0543842a82bb 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -708,7 +708,7 @@ defm "" : ReplaceLane<I64x2, 30>;
 defm "" : ReplaceLane<F32x4, 32>;
 defm "" : ReplaceLane<F64x2, 34>;
 
-// For now use an instrinsic for f16x8.replace_lane instead of ReplaceLane above
+// For now use an intrinsic for f16x8.replace_lane instead of ReplaceLane above
 // since LLVM IR generated with half type arguments is not well supported and
 // creates conversions from f16->f32.
 defm REPLACE_LANE_F16x8 :
diff --git a/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll b/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
index a2d171c173089f..a97ed0a9851e5f 100644
--- a/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
+++ b/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
@@ -54,7 +54,7 @@ define <vscale x 32 x i8> @ld2.nxv32i8_no_eltty(<vscale x 16 x i1> %Pg, i8 *%bas
 ret <vscale x 32 x i8> %res
 }
 
-; ldN instrinsic name with only output type
+; ldN intrinsic name with only output type
 define <vscale x 32 x i8> @ld2.nxv32i8_no_predty_pty(<vscale x 16 x i1> %Pg, i8 *%base_ptr) {
 ; CHECK-LABEL:  @ld2.nxv32i8_no_predty_pty
 ; CHECK:  %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8(<vscale x 16 x i1> %Pg, ptr %base_ptr)
diff --git a/llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll b/llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll
index 56b151d7f9412a..2762b8d3455cb6 100644
--- a/llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test vector add reduction instrinsic
+; Test vector add reduction intrinsic
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s
 
diff --git a/llvm/test/Transforms/JumpThreading/thread-debug-info.ll b/llvm/test/Transforms/JumpThreading/thread-debug-info.ll
index cd7b0b1c05a801..4727413b35a60b 100644
--- a/llvm/test/Transforms/JumpThreading/thread-debug-info.ll
+++ b/llvm/test/Transforms/JumpThreading/thread-debug-info.ll
@@ -50,7 +50,7 @@ exit:                                             ; preds = %bb.f4, %bb.f3, %bb.
   ret void, !dbg !29
 }
 
-; This is testing for debug value instrinsics outside of the threaded block pointing to a value
+; This is testing for debug value intrinsics outside of the threaded block pointing to a value
 ; inside to correctly take any new definitions.
 define void @test2(i32 %cond1, i32 %cond2) !dbg !5 {
 ; CHECK: bb.f3
diff --git a/llvm/test/Transforms/SROA/fake-use-sroa.ll b/llvm/test/Transforms/SROA/fake-use-sroa.ll
index 9e92df15487506..42b0cbb3b0df7f 100644
--- a/llvm/test/Transforms/SROA/fake-use-sroa.ll
+++ b/llvm/test/Transforms/SROA/fake-use-sroa.ll
@@ -1,5 +1,5 @@
 ; RUN: opt -S -passes=sroa %s | FileCheck %s
-; With fake use instrinsics generated for small aggregates, check that when
+; With fake use intrinsics generated for small aggregates, check that when
 ; SROA slices the aggregate, we generate individual fake use intrinsics for
 ; the individual values.
 
diff --git a/llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp b/llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp
index 3ce85f5d7be23e..8fe74e34fe4409 100644
--- a/llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp
+++ b/llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp
@@ -487,7 +487,7 @@ TEST(RandomIRBuilderTest, findSourceAndSink) {
     ASSERT_TRUE(DT.dominates(Insts[IP - 1], Sink));
   }
 }
-TEST(RandomIRBuilderTest, sinkToInstrinsic) {
+TEST(RandomIRBuilderTest, sinkToIntrinsic) {
   const char *Source = "\n\
         declare double @llvm.sqrt.f64(double %Val)  \n\
         declare void   @llvm.ubsantrap(i8 immarg) cold noreturn nounwind  \n\
diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
index a150e2be11736a..984af50a7b0a51 100644
--- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
+++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
@@ -678,7 +678,7 @@ lowerReductionWithStartValue(ConversionPatternRewriter &rewriter, Location loc,
                                           vectorOperand, fmf);
 }
 
-/// Overloaded methods to lower a *predicated* reduction to an llvm instrinsic
+/// Overloaded methods to lower a *predicated* reduction to an llvm intrinsic
 /// that requires a start value. This start value format spans across fp
 /// reductions without mask and all the masked reduction intrinsics.
 template <class LLVMVPRedIntrinOp, class ReductionNeutral>
diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
index 6e97b2a50af8a1..1f63519373ecab 100644
--- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
@@ -2180,7 +2180,7 @@ ModuleImport::processDebugIntrinsic(llvm::DbgVariableIntrinsic *dbgIntr,
     return emitError(loc) << "failed to convert a debug intrinsic operand: "
                           << diag(*dbgIntr);
 
-  // Ensure that the debug instrinsic is inserted right after its operand is
+  // Ensure that the debug intrinsic is inserted right after its operand is
   // defined. Otherwise, the operand might not necessarily dominate the
   // intrinsic. If the defining operation is a terminator, insert the intrinsic
   // into a dominated block.

llvmbot · 2024-10-18T12:56:35Z

@llvm/pr-subscribers-backend-systemz

Author: Jay Foad (jayfoad)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/112899.diff

19 Files Affected:

(modified) clang/utils/TableGen/RISCVVEmitter.cpp (+2-2)
(modified) flang/docs/OptionComparison.md (+1-1)
(modified) flang/include/flang/Runtime/magic-numbers.h (+1-1)
(modified) flang/lib/Evaluate/intrinsics.cpp (+1-1)
(modified) flang/lib/Optimizer/Builder/Runtime/Numeric.cpp (+3-3)
(modified) flang/lib/Optimizer/Builder/Runtime/Reduction.cpp (+1-1)
(modified) lldb/CMakeLists.txt (+1-1)
(modified) llvm/include/llvm/IR/IntrinsicsAMDGPU.td (+1-1)
(modified) llvm/include/llvm/Transforms/Utils/SSAUpdater.h (+1-1)
(modified) llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp (+1-1)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+1-1)
(modified) llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (+1-1)
(modified) llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll (+1-1)
(modified) llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll (+1-1)
(modified) llvm/test/Transforms/JumpThreading/thread-debug-info.ll (+1-1)
(modified) llvm/test/Transforms/SROA/fake-use-sroa.ll (+1-1)
(modified) llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp (+1-1)
(modified) mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp (+1-1)
(modified) mlir/lib/Target/LLVMIR/ModuleImport.cpp (+1-1)

diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index 50f161fd38ce69..aecca0f5df8d93 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -169,7 +169,7 @@ static VectorTypeModifier getTupleVTM(unsigned NF) {
 
 static unsigned getIndexedLoadStorePtrIdx(const RVVIntrinsic *RVVI) {
   // We need a special rule for segment load/store since the data width is not
-  // encoded in the instrinsic name itself.
+  // encoded in the intrinsic name itself.
   const StringRef IRName = RVVI->getIRName();
   constexpr unsigned RVV_VTA = 0x1;
   constexpr unsigned RVV_VMA = 0x2;
@@ -192,7 +192,7 @@ static unsigned getIndexedLoadStorePtrIdx(const RVVIntrinsic *RVVI) {
 static unsigned getSegInstLog2SEW(StringRef InstName) {
   // clang-format off
   // We need a special rule for indexed segment load/store since the data width
-  // is not encoded in the instrinsic name itself.
+  // is not encoded in the intrinsic name itself.
   if (InstName.starts_with("vloxseg") || InstName.starts_with("vluxseg") ||
       InstName.starts_with("vsoxseg") || InstName.starts_with("vsuxseg"))
     return (unsigned)-1;
diff --git a/flang/docs/OptionComparison.md b/flang/docs/OptionComparison.md
index 9d6916ef62af2e..fb65498fa1f444 100644
--- a/flang/docs/OptionComparison.md
+++ b/flang/docs/OptionComparison.md
@@ -53,7 +53,7 @@ eN
    </td>
    <td>fdec,
 <p>
-fall-instrinsics
+fall-intrinsics
    </td>
    <td><a href="https://www-01.ibm.com/support/docview.wss?uid=swg27024803&aid=1#page=297">qxlf77</a>,
 <p>
diff --git a/flang/include/flang/Runtime/magic-numbers.h b/flang/include/flang/Runtime/magic-numbers.h
index bab0e9ae05299a..1d3c5dca0b4bfb 100644
--- a/flang/include/flang/Runtime/magic-numbers.h
+++ b/flang/include/flang/Runtime/magic-numbers.h
@@ -107,7 +107,7 @@ The denorm value is a nonstandard extension.
 
 #if 0
 ieee_round_type values
-The values are those of the llvm.get.rounding instrinsic, which is assumed by
+The values are those of the llvm.get.rounding intrinsic, which is assumed by
 ieee_arithmetic module rounding procedures.
 #endif
 #define _FORTRAN_RUNTIME_IEEE_TO_ZERO 0
diff --git a/flang/lib/Evaluate/intrinsics.cpp b/flang/lib/Evaluate/intrinsics.cpp
index 4271faa0db12bf..aa44967817722e 100644
--- a/flang/lib/Evaluate/intrinsics.cpp
+++ b/flang/lib/Evaluate/intrinsics.cpp
@@ -1690,7 +1690,7 @@ std::optional<SpecificCall> IntrinsicInterface::Match(
   // MAX and MIN (and others that map to them) allow their last argument to
   // be repeated indefinitely.  The actualForDummy vector is sized
   // and null-initialized to the non-repeated dummy argument count
-  // for other instrinsics.
+  // for other intrinsics.
   bool isMaxMin{dummyArgPatterns > 0 &&
       dummy[dummyArgPatterns - 1].optionality == Optionality::repeats};
   std::vector<ActualArgument *> actualForDummy(
diff --git a/flang/lib/Optimizer/Builder/Runtime/Numeric.cpp b/flang/lib/Optimizer/Builder/Runtime/Numeric.cpp
index c13064a284d127..d0092add0118f1 100644
--- a/flang/lib/Optimizer/Builder/Runtime/Numeric.cpp
+++ b/flang/lib/Optimizer/Builder/Runtime/Numeric.cpp
@@ -284,7 +284,7 @@ struct ForcedSpacing16 {
   }
 };
 
-/// Generate call to Exponent instrinsic runtime routine.
+/// Generate call to Exponent intrinsic runtime routine.
 mlir::Value fir::runtime::genExponent(fir::FirOpBuilder &builder,
                                       mlir::Location loc, mlir::Type resultType,
                                       mlir::Value x) {
@@ -320,7 +320,7 @@ mlir::Value fir::runtime::genExponent(fir::FirOpBuilder &builder,
   return builder.create<fir::CallOp>(loc, func, args).getResult(0);
 }
 
-/// Generate call to Fraction instrinsic runtime routine.
+/// Generate call to Fraction intrinsic runtime routine.
 mlir::Value fir::runtime::genFraction(fir::FirOpBuilder &builder,
                                       mlir::Location loc, mlir::Value x) {
   mlir::func::FuncOp func;
@@ -596,7 +596,7 @@ mlir::Value fir::runtime::genSelectedRealKind(fir::FirOpBuilder &builder,
   return builder.create<fir::CallOp>(loc, func, args).getResult(0);
 }
 
-/// Generate call to Set_exponent instrinsic runtime routine.
+/// Generate call to Set_exponent intrinsic runtime routine.
 mlir::Value fir::runtime::genSetExponent(fir::FirOpBuilder &builder,
                                          mlir::Location loc, mlir::Value x,
                                          mlir::Value i) {
diff --git a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
index f6627dff671e6f..b768733bd2fd8f 100644
--- a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
+++ b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp
@@ -1513,7 +1513,7 @@ mlir::Value fir::runtime::genSum(fir::FirOpBuilder &builder, mlir::Location loc,
 
 // The IAll, IAny and IParity intrinsics have essentially the same
 // implementation. This macro will generate the function body given the
-// instrinsic name.
+// intrinsic name.
 #define GEN_IALL_IANY_IPARITY(F)                                               \
   mlir::Value fir::runtime::JOIN2(gen, F)(                                     \
       fir::FirOpBuilder & builder, mlir::Location loc, mlir::Value arrayBox,   \
diff --git a/lldb/CMakeLists.txt b/lldb/CMakeLists.txt
index 59cdc4593463c1..5827e04b5662f3 100644
--- a/lldb/CMakeLists.txt
+++ b/lldb/CMakeLists.txt
@@ -97,7 +97,7 @@ if (LLDB_ENABLE_PYTHON OR LLDB_ENABLE_LUA)
   add_subdirectory(bindings)
 endif ()
 
-# We need the headers generated by instrinsics_gen before we can compile
+# We need the headers generated by intrinsics_gen before we can compile
 # any source file in LLDB as the imported Clang modules might include
 # some of these generated headers. This approach is copied from Clang's main
 # CMakeLists.txt, so it should kept in sync the code in Clang which was added
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 715f2cc917e21c..92226a687cad40 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -1115,7 +1115,7 @@ def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic <
 // it is const 0. A struct intrinsic with constant 0 index is different to the
 // corresponding raw intrinsic on gfx9+ because the behavior of bound checking
 // and swizzling changes depending on whether idxen is set in the instruction.
-// These instrinsics also keep the offset and soffset arguments separate as
+// These intrinsics also keep the offset and soffset arguments separate as
 // they behave differently in bounds checking and swizzling.
 
 // The versions of these intrinsics that take <4 x i32> arguments are deprecated
diff --git a/llvm/include/llvm/Transforms/Utils/SSAUpdater.h b/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
index 29d96a0ab6bf5b..73649766a95388 100644
--- a/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
+++ b/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
@@ -118,7 +118,7 @@ class SSAUpdater {
 
   /// Rewrite debug value intrinsics to conform to a new SSA form.
   ///
-  /// This will scout out all the debug value instrinsics associated with
+  /// This will scout out all the debug value intrinsics associated with
   /// the instruction. Anything outside of its block will have its
   /// value set to the new SSA value if available, and undef if not.
   void UpdateDebugValues(Instruction *I);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
index ee5e75955cd459..e4ca1ae0499b93 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
@@ -580,7 +580,7 @@ std::pair<Value *, Value *> AMDGPUAtomicOptimizerImpl::buildScanIteratively(
   auto *ActiveBits = B.CreatePHI(WaveTy, 2, "ActiveBits");
   ActiveBits->addIncoming(Ballot, EntryBB);
 
-  // Use llvm.cttz instrinsic to find the lowest remaining active lane.
+  // Use llvm.cttz intrinsic to find the lowest remaining active lane.
   auto *FF1 =
       B.CreateIntrinsic(Intrinsic::cttz, WaveTy, {ActiveBits, B.getTrue()});
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 68182d238e7847..6b308bc8c9aa0f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -50,7 +50,7 @@
 /// each of the preceding fields which are relevant for a given instruction
 /// in the opcode space.
 ///
-/// Currently, the policy is represented via the following instrinsic families:
+/// Currently, the policy is represented via the following intrinsic families:
 /// * _MASK - Can represent all three policy states for both tail and mask.  If
 ///   passthrough is IMPLICIT_DEF (or NoReg), then represents "undefined".
 ///   Otherwise, policy operand and tablegen flags drive the interpretation.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 60b3294b5f0bd0..2c0543842a82bb 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -708,7 +708,7 @@ defm "" : ReplaceLane<I64x2, 30>;
 defm "" : ReplaceLane<F32x4, 32>;
 defm "" : ReplaceLane<F64x2, 34>;
 
-// For now use an instrinsic for f16x8.replace_lane instead of ReplaceLane above
+// For now use an intrinsic for f16x8.replace_lane instead of ReplaceLane above
 // since LLVM IR generated with half type arguments is not well supported and
 // creates conversions from f16->f32.
 defm REPLACE_LANE_F16x8 :
diff --git a/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll b/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
index a2d171c173089f..a97ed0a9851e5f 100644
--- a/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
+++ b/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
@@ -54,7 +54,7 @@ define <vscale x 32 x i8> @ld2.nxv32i8_no_eltty(<vscale x 16 x i1> %Pg, i8 *%bas
 ret <vscale x 32 x i8> %res
 }
 
-; ldN instrinsic name with only output type
+; ldN intrinsic name with only output type
 define <vscale x 32 x i8> @ld2.nxv32i8_no_predty_pty(<vscale x 16 x i1> %Pg, i8 *%base_ptr) {
 ; CHECK-LABEL:  @ld2.nxv32i8_no_predty_pty
 ; CHECK:  %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8(<vscale x 16 x i1> %Pg, ptr %base_ptr)
diff --git a/llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll b/llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll
index 56b151d7f9412a..2762b8d3455cb6 100644
--- a/llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-reduce-add-01.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; Test vector add reduction instrinsic
+; Test vector add reduction intrinsic
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s
 
diff --git a/llvm/test/Transforms/JumpThreading/thread-debug-info.ll b/llvm/test/Transforms/JumpThreading/thread-debug-info.ll
index cd7b0b1c05a801..4727413b35a60b 100644
--- a/llvm/test/Transforms/JumpThreading/thread-debug-info.ll
+++ b/llvm/test/Transforms/JumpThreading/thread-debug-info.ll
@@ -50,7 +50,7 @@ exit:                                             ; preds = %bb.f4, %bb.f3, %bb.
   ret void, !dbg !29
 }
 
-; This is testing for debug value instrinsics outside of the threaded block pointing to a value
+; This is testing for debug value intrinsics outside of the threaded block pointing to a value
 ; inside to correctly take any new definitions.
 define void @test2(i32 %cond1, i32 %cond2) !dbg !5 {
 ; CHECK: bb.f3
diff --git a/llvm/test/Transforms/SROA/fake-use-sroa.ll b/llvm/test/Transforms/SROA/fake-use-sroa.ll
index 9e92df15487506..42b0cbb3b0df7f 100644
--- a/llvm/test/Transforms/SROA/fake-use-sroa.ll
+++ b/llvm/test/Transforms/SROA/fake-use-sroa.ll
@@ -1,5 +1,5 @@
 ; RUN: opt -S -passes=sroa %s | FileCheck %s
-; With fake use instrinsics generated for small aggregates, check that when
+; With fake use intrinsics generated for small aggregates, check that when
 ; SROA slices the aggregate, we generate individual fake use intrinsics for
 ; the individual values.
 
diff --git a/llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp b/llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp
index 3ce85f5d7be23e..8fe74e34fe4409 100644
--- a/llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp
+++ b/llvm/unittests/FuzzMutate/RandomIRBuilderTest.cpp
@@ -487,7 +487,7 @@ TEST(RandomIRBuilderTest, findSourceAndSink) {
     ASSERT_TRUE(DT.dominates(Insts[IP - 1], Sink));
   }
 }
-TEST(RandomIRBuilderTest, sinkToInstrinsic) {
+TEST(RandomIRBuilderTest, sinkToIntrinsic) {
   const char *Source = "\n\
         declare double @llvm.sqrt.f64(double %Val)  \n\
         declare void   @llvm.ubsantrap(i8 immarg) cold noreturn nounwind  \n\
diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
index a150e2be11736a..984af50a7b0a51 100644
--- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
+++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
@@ -678,7 +678,7 @@ lowerReductionWithStartValue(ConversionPatternRewriter &rewriter, Location loc,
                                           vectorOperand, fmf);
 }
 
-/// Overloaded methods to lower a *predicated* reduction to an llvm instrinsic
+/// Overloaded methods to lower a *predicated* reduction to an llvm intrinsic
 /// that requires a start value. This start value format spans across fp
 /// reductions without mask and all the masked reduction intrinsics.
 template <class LLVMVPRedIntrinOp, class ReductionNeutral>
diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
index 6e97b2a50af8a1..1f63519373ecab 100644
--- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
@@ -2180,7 +2180,7 @@ ModuleImport::processDebugIntrinsic(llvm::DbgVariableIntrinsic *dbgIntr,
     return emitError(loc) << "failed to convert a debug intrinsic operand: "
                           << diag(*dbgIntr);
 
-  // Ensure that the debug instrinsic is inserted right after its operand is
+  // Ensure that the debug intrinsic is inserted right after its operand is
   // defined. Otherwise, the operand might not necessarily dominate the
   // intrinsic. If the defining operation is a terminator, insert the intrinsic
   // into a dominated block.

cor3ntin

cute typo :)

shiltian

Can't believe this many Lol

banach-space

LGTM, thanks!

I blame my editor's dictionary 😂

Dinistro

LGTM, thanks for the fixes 😄

Fix typo "instrinsic"

3a3b67f

jayfoad requested review from banach-space, dcaballe, nicolasvasilache and JDevlieghere as code owners October 18, 2024 12:56

llvmbot added clang Clang issues not falling into any other category lldb backend:AMDGPU backend:RISC-V backend:SystemZ backend:WebAssembly mlir:llvm mlir flang Flang issues not falling into any other category flang:fir-hlfir llvm:ir llvm:transforms flang:semantics labels Oct 18, 2024

cor3ntin approved these changes Oct 18, 2024

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jayfoad merged commit 922992a into llvm:main Oct 18, 2024
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jayfoad deleted the instrinsic branch October 18, 2024 14:58

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Fix typo "instrinsic" #112899

Fix typo "instrinsic" #112899

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llvmbot commented Oct 18, 2024 •

edited

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Fix typo "instrinsic" #112899

Fix typo "instrinsic" #112899

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