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[AArch64] Add assembly/disassembly for BFMOP4{A,S} (non-widening) instructions #113342

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5 changes: 5 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -1047,3 +1047,8 @@ let Predicates = [HasSME2p2, HasSMEF8F32] in {
defm FMOP4A : sme2_fmop4a_fp8_fp32_4way<"fmop4a">;
}
}

let Predicates = [HasSME2p2, HasSMEB16B16] in {
defm BFMOP4A : sme2_bfmop4as_non_widening<0, "bfmop4a">;
defm BFMOP4S : sme2_bfmop4as_non_widening<1, "bfmop4s">;
}
37 changes: 37 additions & 0 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
Original file line number Diff line number Diff line change
Expand Up @@ -5417,3 +5417,40 @@ multiclass sme2_fmop4a_fp8_fp32_4way<string mnemonic> {
// Multiple vectors
def _M2Z2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>;
}

class sme2_bf16_fp16_quarter_tile_outer_product<bit M, bit N, bit S, string mnemonic, RegisterOperand zn_ty, RegisterOperand zm_ty>
: I<(outs TileOp16:$ZAda),
(ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm),
mnemonic, "\t$ZAda, $Zn, $Zm",
"", []>, Sched<[]> {
bit ZAda;
bits<3> Zn;
bits<3> Zm;

let Inst{31-21} = 0b10000001001;
let Inst{20} = M;
let Inst{19-17} = Zm;
let Inst{16-10} = 0b0000000;
let Inst{9} = N;
let Inst{8-6} = Zn;
let Inst{5} = 0;
let Inst{4} = S;
let Inst{3-1} = 0b100;
let Inst{0} = ZAda;

let Constraints = "$ZAda = $_ZAda";
}

multiclass sme2_bfmop4as_non_widening<bit S, string mnemonic> {
// Single vectors
def _MZZ_H : sme2_bf16_fp16_quarter_tile_outer_product<0, 0, S, mnemonic, ZPR16Mul2_Lo, ZPR16Mul2_Hi>;

// Multiple and single vectors
def _M2ZZ_H : sme2_bf16_fp16_quarter_tile_outer_product<0, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZPR16Mul2_Hi>;

// Single and multiple vectors
def _MZ2Z_H : sme2_bf16_fp16_quarter_tile_outer_product<1, 0, S, mnemonic, ZPR16Mul2_Lo, ZZ_h_mul_r_Hi>;

// Multiple vectors
def _M2Z2Z_H : sme2_bf16_fp16_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>;
}
220 changes: 220 additions & 0 deletions llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,220 @@
// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 < %s 2>&1 | FileCheck %s

// BFMOP4A

// Single vectors

bfmop4a za0.d, z0.h, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s

bfmop4a za4.h, z0.h, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4a za0.h, z0.s, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4a za0.h, z15.h, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4a za0.h, z16.h, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4a za0.h, z0.h, z16.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4a za0.h, z12.h, z17.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4a za0.h, z12.h, z14.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4a za0.h, z12.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

// Single and multiple vectors

bfmop4a za0.d, z0.h, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s

bfmop4a za4.h, z0.h, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4a za0.h, z0.s, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4a za0.h, z1.h, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4a za0.h, z16.h, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4a za0.h, z0.h, {z16.s-z17.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4a za0.h, z0.h, {z17.h-z18.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

bfmop4a za0.h, z0.h, {z12.h-z13.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

// Multiple and single vectors

bfmop4a za0.d, {z0.h-z1.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s

bfmop4a za4.h, {z0.h-z1.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4a za0.h, {z0.s-z1.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix

bfmop4a za0.h, {z1.h-z2.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types

bfmop4a za0.h, {z16.h-z17.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types

bfmop4a za0.h, {z0.h-z1.h}, z16.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4a za0.h, {z0.h-z1.h}, z17.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4a za0.h, {z0.h-z1.h}, z12.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

// Multiple vectors

bfmop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s

bfmop4a za4.h, {z0.h-z1.h}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4a za0.h, {z0.s-z1.s}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4a za0.h, {z1.h-z2.h}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types

bfmop4a za0.h, {z18.h-z19.h}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types

bfmop4a za0.h, {z0.h-z1.h}, {z16.s-z17.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4a za0.h, {z0.h-z1.h}, {z19.h-z20.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

bfmop4a za0.h, {z0.h-z1.h}, {z10.h-z11.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types


// BFMOP4S

// Single vectors

bfmop4s za0.d, z0.h, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s

bfmop4s za4.h, z0.h, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4s za0.h, z0.s, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4s za0.h, z15.h, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4s za0.h, z16.h, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4s za0.h, z0.h, z16.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4s za0.h, z12.h, z17.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4s za0.h, z12.h, z14.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4s za0.h, z12.h, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

// Single and multiple vectors

bfmop4s za0.d, z0.h, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s

bfmop4s za4.h, z0.h, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4s za0.h, z0.s, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4s za0.h, z1.h, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4s za0.h, z16.h, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h

bfmop4s za0.h, z0.h, {z16.s-z17.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4s za0.h, z0.h, {z17.h-z18.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

bfmop4s za0.h, z0.h, {z12.h-z13.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

// Multiple and single vectors

bfmop4s za0.d, {z0.h-z1.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s

bfmop4s za4.h, {z0.h-z1.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4s za0.h, {z0.s-z1.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix

bfmop4s za0.h, {z1.h-z2.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types

bfmop4s za0.h, {z16.h-z17.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types

bfmop4s za0.h, {z0.h-z1.h}, z16.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4s za0.h, {z0.h-z1.h}, z17.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

bfmop4s za0.h, {z0.h-z1.h}, z12.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h

// Multiple vectors

bfmop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s

bfmop4s za4.h, {z0.h-z1.h}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4s za0.h, {z0.s-z1.s}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4s za0.h, {z1.h-z2.h}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types

bfmop4s za0.h, {z18.h-z19.h}, {z16.h-z17.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types

bfmop4s za0.h, {z0.h-z1.h}, {z16.s-z17.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

bfmop4s za0.h, {z0.h-z1.h}, {z19.h-z20.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types

bfmop4s za0.h, {z0.h-z1.h}, {z10.h-z11.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types
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