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[LoongArch] Enable FeatureExtLSX for generic-la64 processor #113421

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Oct 31, 2024
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[LoongArch] Enable FeatureExtLSX for generic-la64 processor #113421

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4 changes: 3 additions & 1 deletion llvm/lib/Target/LoongArch/LoongArch.td
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Expand Up @@ -129,7 +129,9 @@ include "LoongArchInstrInfo.td"
//===----------------------------------------------------------------------===//

def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>;
def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, FeatureUAL]>;
def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit,
FeatureUAL,
FeatureExtLSX]>;

// Generic 64-bit processor with double-precision floating-point support.
def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit,
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18 changes: 8 additions & 10 deletions llvm/test/CodeGen/LoongArch/calling-conv-common.ll
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Expand Up @@ -123,13 +123,12 @@ define i64 @caller_large_scalars() nounwind {
; CHECK-NEXT: addi.d $sp, $sp, -80
; CHECK-NEXT: st.d $ra, $sp, 72 # 8-byte Folded Spill
; CHECK-NEXT: st.d $zero, $sp, 24
; CHECK-NEXT: st.d $zero, $sp, 16
; CHECK-NEXT: st.d $zero, $sp, 8
; CHECK-NEXT: vrepli.b $vr0, 0
; CHECK-NEXT: vst $vr0, $sp, 8
; CHECK-NEXT: ori $a0, $zero, 2
; CHECK-NEXT: st.d $a0, $sp, 0
; CHECK-NEXT: st.d $zero, $sp, 56
; CHECK-NEXT: st.d $zero, $sp, 48
; CHECK-NEXT: st.d $zero, $sp, 40
; CHECK-NEXT: vst $vr0, $sp, 40
; CHECK-NEXT: ori $a2, $zero, 1
; CHECK-NEXT: addi.d $a0, $sp, 32
; CHECK-NEXT: addi.d $a1, $sp, 0
Expand Down Expand Up @@ -182,14 +181,13 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; CHECK-NEXT: ori $a0, $zero, 9
; CHECK-NEXT: st.d $a0, $sp, 0
; CHECK-NEXT: st.d $zero, $sp, 40
; CHECK-NEXT: st.d $zero, $sp, 32
; CHECK-NEXT: st.d $zero, $sp, 24
; CHECK-NEXT: vrepli.b $vr0, 0
; CHECK-NEXT: vst $vr0, $sp, 24
; CHECK-NEXT: ori $a0, $zero, 10
; CHECK-NEXT: st.d $a0, $sp, 16
; CHECK-NEXT: st.d $zero, $sp, 72
; CHECK-NEXT: st.d $zero, $sp, 64
; CHECK-NEXT: st.d $zero, $sp, 56
; CHECK-NEXT: ori $t0, $zero, 8
; CHECK-NEXT: ori $a0, $zero, 8
; CHECK-NEXT: st.d $a0, $sp, 48
; CHECK-NEXT: ori $a0, $zero, 1
; CHECK-NEXT: ori $a1, $zero, 2
; CHECK-NEXT: ori $a2, $zero, 3
Expand All @@ -198,7 +196,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; CHECK-NEXT: ori $a5, $zero, 6
; CHECK-NEXT: ori $a6, $zero, 7
; CHECK-NEXT: addi.d $a7, $sp, 48
; CHECK-NEXT: st.d $t0, $sp, 48
; CHECK-NEXT: vst $vr0, $sp, 56
; CHECK-NEXT: bl %plt(callee_large_scalars_exhausted_regs)
; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 96
Expand Down
29 changes: 9 additions & 20 deletions llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
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Expand Up @@ -63,26 +63,17 @@ define i64 @caller_double_in_gpr_exhausted_fprs() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
; CHECK-NEXT: fld.d $fa1, $a0, %pc_lo12(.LCPI3_0)
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_1)
; CHECK-NEXT: fld.d $fa2, $a0, %pc_lo12(.LCPI3_1)
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_2)
; CHECK-NEXT: fld.d $fa3, $a0, %pc_lo12(.LCPI3_2)
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_3)
; CHECK-NEXT: fld.d $fa4, $a0, %pc_lo12(.LCPI3_3)
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_4)
; CHECK-NEXT: fld.d $fa5, $a0, %pc_lo12(.LCPI3_4)
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_5)
; CHECK-NEXT: fld.d $fa6, $a0, %pc_lo12(.LCPI3_5)
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_6)
; CHECK-NEXT: fld.d $fa7, $a0, %pc_lo12(.LCPI3_6)
; CHECK-NEXT: addi.d $a0, $zero, 1
; CHECK-NEXT: movgr2fr.d $fa0, $a0
; CHECK-NEXT: ffint.d.l $fa0, $fa0
; CHECK-NEXT: ori $a0, $zero, 0
; CHECK-NEXT: lu32i.d $a0, 131072
; CHECK-NEXT: lu52i.d $a0, $a0, 1026
; CHECK-NEXT: vldi $vr0, -912
; CHECK-NEXT: vldi $vr1, -1024
; CHECK-NEXT: vldi $vr2, -1016
; CHECK-NEXT: vldi $vr3, -1008
; CHECK-NEXT: vldi $vr4, -1004
; CHECK-NEXT: vldi $vr5, -1000
; CHECK-NEXT: vldi $vr6, -996
; CHECK-NEXT: vldi $vr7, -992
; CHECK-NEXT: bl %plt(callee_double_in_gpr_exhausted_fprs)
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
Expand All @@ -98,9 +89,7 @@ define i64 @caller_double_in_gpr_exhausted_fprs() nounwind {
define double @callee_double_ret() nounwind {
; CHECK-LABEL: callee_double_ret:
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $a0, $zero, 1
; CHECK-NEXT: movgr2fr.d $fa0, $a0
; CHECK-NEXT: ffint.d.l $fa0, $fa0
; CHECK-NEXT: vldi $vr0, -912
; CHECK-NEXT: ret
ret double 1.0
}
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/LoongArch/calling-conv-lp64s.ll
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@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc --mtriple=loongarch64 --target-abi=lp64s < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --target-abi=lp64s --mattr=-f < %s | FileCheck %s

;; This file contains specific tests for the lp64s ABI.

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89 changes: 19 additions & 70 deletions llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
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Expand Up @@ -175,16 +175,11 @@ define i8 @test_ctpop_i8(i8 %a) nounwind {
;
; LA64-LABEL: test_ctpop_i8:
; LA64: # %bb.0:
; LA64-NEXT: srli.d $a1, $a0, 1
; LA64-NEXT: andi $a1, $a1, 85
; LA64-NEXT: sub.d $a0, $a0, $a1
; LA64-NEXT: andi $a1, $a0, 51
; LA64-NEXT: srli.d $a0, $a0, 2
; LA64-NEXT: andi $a0, $a0, 51
; LA64-NEXT: add.d $a0, $a1, $a0
; LA64-NEXT: srli.d $a1, $a0, 4
; LA64-NEXT: add.d $a0, $a0, $a1
; LA64-NEXT: andi $a0, $a0, 15
; LA64-NEXT: andi $a0, $a0, 255
; LA64-NEXT: vldi $vr0, 0
; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
; LA64-NEXT: vpcnt.d $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
; LA64-NEXT: ret
%1 = call i8 @llvm.ctpop.i8(i8 %a)
ret i8 %1
Expand Down Expand Up @@ -213,22 +208,11 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
;
; LA64-LABEL: test_ctpop_i16:
; LA64: # %bb.0:
; LA64-NEXT: srli.d $a1, $a0, 1
; LA64-NEXT: lu12i.w $a2, 5
; LA64-NEXT: ori $a2, $a2, 1365
; LA64-NEXT: and $a1, $a1, $a2
; LA64-NEXT: sub.d $a0, $a0, $a1
; LA64-NEXT: lu12i.w $a1, 3
; LA64-NEXT: ori $a1, $a1, 819
; LA64-NEXT: and $a2, $a0, $a1
; LA64-NEXT: srli.d $a0, $a0, 2
; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: add.d $a0, $a2, $a0
; LA64-NEXT: srli.d $a1, $a0, 4
; LA64-NEXT: add.d $a0, $a0, $a1
; LA64-NEXT: bstrpick.d $a1, $a0, 11, 8
; LA64-NEXT: andi $a0, $a0, 15
; LA64-NEXT: add.d $a0, $a0, $a1
; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
; LA64-NEXT: vldi $vr0, 0
; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
; LA64-NEXT: vpcnt.d $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
; LA64-NEXT: ret
%1 = call i16 @llvm.ctpop.i16(i16 %a)
ret i16 %1
Expand Down Expand Up @@ -261,26 +245,11 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
;
; LA64-LABEL: test_ctpop_i32:
; LA64: # %bb.0:
; LA64-NEXT: srli.d $a1, $a0, 1
; LA64-NEXT: lu12i.w $a2, 349525
; LA64-NEXT: ori $a2, $a2, 1365
; LA64-NEXT: and $a1, $a1, $a2
; LA64-NEXT: sub.d $a0, $a0, $a1
; LA64-NEXT: lu12i.w $a1, 209715
; LA64-NEXT: ori $a1, $a1, 819
; LA64-NEXT: and $a2, $a0, $a1
; LA64-NEXT: srli.d $a0, $a0, 2
; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: add.d $a0, $a2, $a0
; LA64-NEXT: srli.d $a1, $a0, 4
; LA64-NEXT: add.d $a0, $a0, $a1
; LA64-NEXT: lu12i.w $a1, 61680
; LA64-NEXT: ori $a1, $a1, 3855
; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: lu12i.w $a1, 4112
; LA64-NEXT: ori $a1, $a1, 257
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: bstrpick.d $a0, $a0, 31, 24
; LA64-NEXT: bstrpick.d $a0, $a0, 31, 0
; LA64-NEXT: vldi $vr0, 0
; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
; LA64-NEXT: vpcnt.d $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
; LA64-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1
Expand Down Expand Up @@ -327,30 +296,10 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
;
; LA64-LABEL: test_ctpop_i64:
; LA64: # %bb.0:
; LA64-NEXT: srli.d $a1, $a0, 1
; LA64-NEXT: lu12i.w $a2, 349525
; LA64-NEXT: ori $a2, $a2, 1365
; LA64-NEXT: bstrins.d $a2, $a2, 62, 32
; LA64-NEXT: and $a1, $a1, $a2
; LA64-NEXT: sub.d $a0, $a0, $a1
; LA64-NEXT: lu12i.w $a1, 209715
; LA64-NEXT: ori $a1, $a1, 819
; LA64-NEXT: bstrins.d $a1, $a1, 61, 32
; LA64-NEXT: and $a2, $a0, $a1
; LA64-NEXT: srli.d $a0, $a0, 2
; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: add.d $a0, $a2, $a0
; LA64-NEXT: srli.d $a1, $a0, 4
; LA64-NEXT: add.d $a0, $a0, $a1
; LA64-NEXT: lu12i.w $a1, 61680
; LA64-NEXT: ori $a1, $a1, 3855
; LA64-NEXT: bstrins.d $a1, $a1, 59, 32
; LA64-NEXT: and $a0, $a0, $a1
; LA64-NEXT: lu12i.w $a1, 4112
; LA64-NEXT: ori $a1, $a1, 257
; LA64-NEXT: bstrins.d $a1, $a1, 56, 32
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: srli.d $a0, $a0, 56
; LA64-NEXT: vldi $vr0, 0
; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
; LA64-NEXT: vpcnt.d $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
; LA64-NEXT: ret
%1 = call i64 @llvm.ctpop.i64(i64 %a)
ret i64 %1
Expand Down
8 changes: 2 additions & 6 deletions llvm/test/CodeGen/LoongArch/double-imm.ll
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Expand Up @@ -59,9 +59,7 @@ define double @f64_add_fimm1(double %a) nounwind {
;
; LA64-LABEL: f64_add_fimm1:
; LA64: # %bb.0:
; LA64-NEXT: addi.d $a0, $zero, 1
; LA64-NEXT: movgr2fr.d $fa1, $a0
; LA64-NEXT: ffint.d.l $fa1, $fa1
; LA64-NEXT: vldi $vr1, -912
; LA64-NEXT: fadd.d $fa0, $fa0, $fa1
; LA64-NEXT: ret
%1 = fadd double %a, 1.0
Expand All @@ -79,9 +77,7 @@ define double @f64_positive_fimm1() nounwind {
;
; LA64-LABEL: f64_positive_fimm1:
; LA64: # %bb.0:
; LA64-NEXT: addi.d $a0, $zero, 1
; LA64-NEXT: movgr2fr.d $fa0, $a0
; LA64-NEXT: ffint.d.l $fa0, $fa0
; LA64-NEXT: vldi $vr0, -912
; LA64-NEXT: ret
ret double 1.0
}
15 changes: 7 additions & 8 deletions llvm/test/CodeGen/LoongArch/fdiv-reciprocal-estimate.ll
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Expand Up @@ -66,14 +66,13 @@ define double @fdiv_d(double %x, double %y) {
;
; LA64D-FRECIPE-LABEL: fdiv_d:
; LA64D-FRECIPE: # %bb.0:
; LA64D-FRECIPE-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
; LA64D-FRECIPE-NEXT: fld.d $fa2, $a0, %pc_lo12(.LCPI1_0)
; LA64D-FRECIPE-NEXT: frecipe.d $fa3, $fa1
; LA64D-FRECIPE-NEXT: fmadd.d $fa2, $fa1, $fa3, $fa2
; LA64D-FRECIPE-NEXT: fnmsub.d $fa2, $fa2, $fa3, $fa3
; LA64D-FRECIPE-NEXT: fmul.d $fa3, $fa0, $fa2
; LA64D-FRECIPE-NEXT: fnmsub.d $fa0, $fa1, $fa3, $fa0
; LA64D-FRECIPE-NEXT: fmadd.d $fa0, $fa2, $fa0, $fa3
; LA64D-FRECIPE-NEXT: frecipe.d $fa2, $fa1
; LA64D-FRECIPE-NEXT: vldi $vr3, -784
; LA64D-FRECIPE-NEXT: fmadd.d $fa3, $fa1, $fa2, $fa3
; LA64D-FRECIPE-NEXT: fnmsub.d $fa2, $fa3, $fa2, $fa2
; LA64D-FRECIPE-NEXT: fmul.d $fa3, $fa0, $fa2
; LA64D-FRECIPE-NEXT: fnmsub.d $fa0, $fa1, $fa3, $fa0
; LA64D-FRECIPE-NEXT: fmadd.d $fa0, $fa2, $fa0, $fa3
; LA64D-FRECIPE-NEXT: ret
%div = fdiv fast double %x, %y
ret double %div
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/LoongArch/frame.ll
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Expand Up @@ -12,8 +12,8 @@ define i32 @test() nounwind {
; CHECK-NEXT: addi.d $sp, $sp, -32
; CHECK-NEXT: st.d $ra, $sp, 24 # 8-byte Folded Spill
; CHECK-NEXT: st.w $zero, $sp, 16
; CHECK-NEXT: st.d $zero, $sp, 8
; CHECK-NEXT: st.d $zero, $sp, 0
; CHECK-NEXT: vrepli.b $vr0, 0
; CHECK-NEXT: vst $vr0, $sp, 0
; CHECK-NEXT: addi.d $a0, $sp, 4
; CHECK-NEXT: bl %plt(test1)
; CHECK-NEXT: move $a0, $zero
Expand Down
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