llvm · lei137 · Oct 23, 2024 · Oct 23, 2024
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -17367,36 +17367,25 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
   return FrameAddr;
 }
 
-#define GET_REGISTER_MATCHER
-#include "PPCGenAsmMatcher.inc"
-
-Register PPCTargetLowering::getRegisterByName(const char *RegName, LLT VT,
+// FIXME? Maybe this could be a TableGen attribute on some registers and
+// this table could be generated automatically from RegInfo.
+Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT,
                                               const MachineFunction &MF) const {
-  bool IsPPC64 = Subtarget.isPPC64();
+  bool isPPC64 = Subtarget.isPPC64();
 
-  bool Is64Bit = IsPPC64 && VT == LLT::scalar(64);
-  if (!Is64Bit && VT != LLT::scalar(32))
+  bool is64Bit = isPPC64 && VT == LLT::scalar(64);
+  if (!is64Bit && VT != LLT::scalar(32))
     report_fatal_error("Invalid register global variable type");
 
-  Register Reg = MatchRegisterName(RegName);
-  if (!Reg)
-    report_fatal_error(
-        Twine("Invalid global name register \"" + StringRef(RegName) + "\"."));
-
-  // FIXME: These registers are not flagged as reserved and we can generate
-  // code for `-O0` but not for `-O2`.  Need followup investigation as to why.
-  if ((IsPPC64 && Reg == PPC::R2) || Reg == PPC::R0)
-    report_fatal_error(Twine("Trying to reserve an invalid register \"" +
-                             StringRef(RegName) + "\"."));
-
-  // Convert GPR to GP8R register for 64bit.
-  if (Is64Bit && StringRef(RegName).starts_with_insensitive("r"))
-    Reg = Reg.id() - PPC::R0 + PPC::X0;
-
-  if (Subtarget.getRegisterInfo()->getReservedRegs(MF).test(Reg))
-    report_fatal_error(Twine("Trying to obtain a reserved register \"" +
-                             StringRef(RegName) + "\"."));
-  return Reg;
+  Register Reg = StringSwitch<Register>(RegName)
+                     .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
+                     .Case("r2", isPPC64 ? Register() : PPC::R2)
+                     .Case("r13", (is64Bit ? PPC::X13 : PPC::R13))
+                     .Default(Register());
+
+  if (Reg)
+    return Reg;
+  report_fatal_error("Invalid register name global variable");
 }
 
 bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const {

diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll
@@ -1,9 +1,11 @@
-; RUN: not --crash llc -O0 < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
-; RUN: not --crash llc -O0 < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 
 define i32 @get_reg() nounwind {
 entry:
-; CHECK: Trying to reserve an invalid register "r0".
+; FIXME: Include an allocatable-specific error message
+; CHECK: Invalid register name global variable
         %reg = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %reg
 }

diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r1-64.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r1-64.ll
@@ -1,10 +1,12 @@
-; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 
 define i64 @get_reg() nounwind {
-; CHECK: Trying to obtain a reserved register "r1".
 entry:
   %reg = call i64 @llvm.read_register.i64(metadata !0)
   ret i64 %reg
+
+; CHECK-LABEL: get_reg
+; CHECK: mr 3, 1
 }
 
 declare i64 @llvm.read_register.i64(metadata) nounwind

diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r1.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r1.ll
@@ -1,11 +1,14 @@
-; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
-; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 
 define i32 @get_reg() nounwind {
-; CHECK: Trying to obtain a reserved register "r1".
 entry:
   %reg = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %reg
+
+; CHECK-LABEL: @get_reg
+; CHECK: mr 3, 1
+
 }
 
 declare i32 @llvm.read_register.i32(metadata) nounwind

diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r13-64.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r13-64.ll
@@ -1,10 +1,13 @@
-; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 
 define i64 @get_reg() nounwind {
-; CHECK: Trying to obtain a reserved register "r13".
 entry:
   %reg = call i64 @llvm.read_register.i64(metadata !0)
   ret i64 %reg
+
+; CHECK-LABEL: @get_reg
+; CHECK: mr 3, 13
+
 }
 
 declare i64 @llvm.read_register.i64(metadata) nounwind

diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r13.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r13.ll
@@ -1,11 +1,13 @@
-; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
-; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 
 define i32 @get_reg() nounwind {
-; CHECK: Trying to obtain a reserved register "r13".
 entry:
         %reg = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %reg
+
+; CHECK-LABEL: @get_reg
+; CHECK: mr 3, 13
 }
 
 declare i32 @llvm.read_register.i32(metadata) nounwind

diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll
@@ -1,8 +1,10 @@
 ; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
 
 define i64 @get_reg() nounwind {
 entry:
-; CHECK: Trying to reserve an invalid register "r2".
+; FIXME: Include an allocatable-specific error message
+; CHECK: Invalid register name global variable
         %reg = call i64 @llvm.read_register.i64(metadata !0)
   ret i64 %reg
 }

diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll
@@ -1,12 +1,15 @@
-; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
 ; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32
 
 define i32 @get_reg() nounwind {
 entry:
-; CHECK-NOTPPC32: Trying to reserve an invalid register "r2".
-; CHECK: Trying to obtain a reserved register "r2".
+; FIXME: Include an allocatable-specific error message
+; CHECK-NOTPPC32: Invalid register name global variable
         %reg = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %reg
+
+; CHECK-LABEL: @get_reg
+; CHECK: mr 3, 2
 }
 
 declare i32 @llvm.read_register.i32(metadata) nounwind

diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc.ll