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Merged
merged 3 commits into from
Oct 28, 2024
Merged

Remove optimization flags from clang codegen tests #113714

merged 3 commits into from
Oct 28, 2024

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MatzeB
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@MatzeB MatzeB commented Oct 25, 2024

  • Remove an -O3 flag from a couple of clang x86 codegen tests so the
    tests do not need to be updated when optimizations in LLVM change.
  • Change the tests to use utils/update_cc_test_checks.sh
  • Change from apple/darwin triples to generic x86_64-- and
    i386-- because it was not relevant to the test but
    update_cc_test_checks seems to be unable to handle platforms that
    prepend _ to function names.

@MatzeB
Remove -O3 in clang codegen test
5c47d3e 
- Remove an -O3 flag from a couple of clang x86 codegen tests so the
  tests do not need to be updated when optimizations in LLVM change.
- Change the tests to use utils/update_cc_test_checks.sh
- Change from apple/darwin triples to generic x86_64-- and
  i386-- because it was not relevant to the test but
  `update_cc_test_checks` seems to be unable to handle platforms that
  prepend `_` to function names.
@llvmbot llvmbot added clang Clang issues not falling into any other category backend:X86 labels Oct 25, 2024
@MatzeB
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MatzeB commented Oct 25, 2024

Update clang tests separately as suggested in #113212

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llvmbot commented Oct 25, 2024 •
edited
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@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-x86

Author: Matthias Braun (MatzeB)

Changes
  • Remove an -O3 flag from a couple of clang x86 codegen tests so the
    tests do not need to be updated when optimizations in LLVM change.
  • Change the tests to use utils/update_cc_test_checks.sh
  • Change from apple/darwin triples to generic x86_64-- and
    i386-- because it was not relevant to the test but
    update_cc_test_checks seems to be unable to handle platforms that
    prepend _ to function names.

Patch is 117.95 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113714.diff

4 Files Affected:

  • (modified) clang/test/CodeGen/X86/avx-cast-builtins.c (+178-49)
  • (modified) clang/test/CodeGen/X86/avx-cmp-builtins.c (+653-20)
  • (modified) clang/test/CodeGen/X86/avx-shuffle-builtins.c (+533-72)
  • (modified) clang/test/CodeGen/X86/sse.c (+62-14)
diff --git a/clang/test/CodeGen/X86/avx-cast-builtins.c b/clang/test/CodeGen/X86/avx-cast-builtins.c
index 8b941c4287b9a0..4dcd371471f4ad 100644
--- a/clang/test/CodeGen/X86/avx-cast-builtins.c
+++ b/clang/test/CodeGen/X86/avx-cast-builtins.c
@@ -1,101 +1,230 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
 // REQUIRES: x86-registered-target
-// RUN: %clang_cc1 -O3 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx -target-feature +avx512f  -target-feature +avx512fp16 -S -o - | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx -target-feature +avx512f  -target-feature +avx512fp16 -emit-llvm -o - | FileCheck %s
 
 
 #include <immintrin.h>
 
+// CHECK-LABEL: define dso_local <4 x double> @test_mm256_castpd128_pd256(
+// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    store <2 x double> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x double> [[TMP0]], ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x double>, ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = freeze <2 x double> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT:    ret <4 x double> [[SHUFFLE_I]]
+//
 __m256d test_mm256_castpd128_pd256(__m128d A) {
-  // CHECK-LABEL: test_mm256_castpd128_pd256
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm256_castpd128_pd256(A);
 }
 
+// CHECK-LABEL: define dso_local <8 x float> @test_mm256_castps128_ps256(
+// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    store <4 x float> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x float> [[TMP0]], ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = freeze <4 x float> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT:    ret <8 x float> [[SHUFFLE_I]]
+//
 __m256 test_mm256_castps128_ps256(__m128 A) {
-  // CHECK-LABEL: test_mm256_castps128_ps256
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm256_castps128_ps256(A);
 }
 
+// CHECK-LABEL: define dso_local <4 x i64> @test_mm256_castsi128_si256(
+// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    store <2 x i64> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x i64> [[TMP0]], ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = freeze <2 x i64> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT:    ret <4 x i64> [[SHUFFLE_I]]
+//
 __m256i test_mm256_castsi128_si256(__m128i A) {
-  // CHECK-LABEL: test_mm256_castsi128_si256
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm256_castsi128_si256(A);
 }
 
+// CHECK-LABEL: define dso_local <16 x half> @test_mm256_castph128_ph256(
+// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <8 x half>, align 16
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <8 x half>, align 16
+// CHECK-NEXT:    store <8 x half> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x half>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x half> [[TMP0]], ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x half>, ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = freeze <8 x half> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> [[TMP2]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+// CHECK-NEXT:    ret <16 x half> [[SHUFFLE_I]]
+//
 __m256h test_mm256_castph128_ph256(__m128h A) {
-  // CHECK-LABEL: test_mm256_castph128_ph256
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm256_castph128_ph256(A);
 }
 
+// CHECK-LABEL: define dso_local <32 x half> @test_mm512_castph128_ph512(
+// CHECK-SAME: <8 x half> noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <8 x half>, align 16
+// CHECK-NEXT:    [[__B_I:%.*]] = alloca <16 x half>, align 32
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <8 x half>, align 16
+// CHECK-NEXT:    store <8 x half> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x half>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <8 x half> [[TMP0]], ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = freeze <16 x half> poison
+// CHECK-NEXT:    store <16 x half> [[TMP1]], ptr [[__B_I]], align 32
+// CHECK-NEXT:    [[TMP2:%.*]] = load <8 x half>, ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP3:%.*]] = freeze <8 x half> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <8 x half> [[TMP2]], <8 x half> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+// CHECK-NEXT:    [[TMP4:%.*]] = load <16 x half>, ptr [[__B_I]], align 32
+// CHECK-NEXT:    [[SHUFFLE1_I:%.*]] = shufflevector <16 x half> [[SHUFFLE_I]], <16 x half> [[TMP4]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+// CHECK-NEXT:    ret <32 x half> [[SHUFFLE1_I]]
+//
 __m512h test_mm512_castph128_ph512(__m128h A) {
-  // CHECK-LABEL: test_mm512_castph128_ph512
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castph128_ph512(A);
 }
 
+// CHECK-LABEL: define dso_local <32 x half> @test_mm512_castph256_ph512(
+// CHECK-SAME: <16 x half> noundef [[A:%.*]]) #[[ATTR1]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <16 x half>, align 32
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <16 x half>, align 32
+// CHECK-NEXT:    store <16 x half> [[A]], ptr [[A_ADDR]], align 32
+// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 32
+// CHECK-NEXT:    store <16 x half> [[TMP0]], ptr [[__A_ADDR_I]], align 32
+// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x half>, ptr [[__A_ADDR_I]], align 32
+// CHECK-NEXT:    [[TMP2:%.*]] = freeze <16 x half> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <16 x half> [[TMP1]], <16 x half> [[TMP2]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+// CHECK-NEXT:    ret <32 x half> [[SHUFFLE_I]]
+//
 __m512h test_mm512_castph256_ph512(__m256h A) {
-  // CHECK-LABEL: test_mm512_castph256_ph512
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castph256_ph512(A);
 }
 
+// CHECK-LABEL: define dso_local <8 x double> @test_mm512_castpd256_pd512(
+// CHECK-SAME: <4 x double> noundef [[A:%.*]]) #[[ATTR1]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <4 x double>, align 32
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <4 x double>, align 32
+// CHECK-NEXT:    store <4 x double> [[A]], ptr [[A_ADDR]], align 32
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x double>, ptr [[A_ADDR]], align 32
+// CHECK-NEXT:    store <4 x double> [[TMP0]], ptr [[__A_ADDR_I]], align 32
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x double>, ptr [[__A_ADDR_I]], align 32
+// CHECK-NEXT:    [[TMP2:%.*]] = freeze <4 x double> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT:    ret <8 x double> [[SHUFFLE_I]]
+//
 __m512d test_mm512_castpd256_pd512(__m256d A){
-  // CHECK-LABEL: test_mm512_castpd256_pd512
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castpd256_pd512(A);
 }
 
+// CHECK-LABEL: define dso_local <16 x float> @test_mm512_castps256_ps512(
+// CHECK-SAME: <8 x float> noundef [[A:%.*]]) #[[ATTR1]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <8 x float>, align 32
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <8 x float>, align 32
+// CHECK-NEXT:    store <8 x float> [[A]], ptr [[A_ADDR]], align 32
+// CHECK-NEXT:    [[TMP0:%.*]] = load <8 x float>, ptr [[A_ADDR]], align 32
+// CHECK-NEXT:    store <8 x float> [[TMP0]], ptr [[__A_ADDR_I]], align 32
+// CHECK-NEXT:    [[TMP1:%.*]] = load <8 x float>, ptr [[__A_ADDR_I]], align 32
+// CHECK-NEXT:    [[TMP2:%.*]] = freeze <8 x float> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+// CHECK-NEXT:    ret <16 x float> [[SHUFFLE_I]]
+//
 __m512 test_mm512_castps256_ps512(__m256 A){
-  // CHECK-LABEL: test_mm512_castps256_ps512
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castps256_ps512(A);
 }
 
+// CHECK-LABEL: define dso_local <8 x double> @test_mm512_castpd128_pd512(
+// CHECK-SAME: <2 x double> noundef [[A:%.*]]) #[[ATTR1]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    [[__B_I:%.*]] = alloca <4 x double>, align 32
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    store <2 x double> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x double> [[TMP0]], ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = freeze <4 x double> poison
+// CHECK-NEXT:    store <4 x double> [[TMP1]], ptr [[__B_I]], align 32
+// CHECK-NEXT:    [[TMP2:%.*]] = load <2 x double>, ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP3:%.*]] = freeze <2 x double> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT:    [[TMP4:%.*]] = load <4 x double>, ptr [[__B_I]], align 32
+// CHECK-NEXT:    [[SHUFFLE1_I:%.*]] = shufflevector <4 x double> [[SHUFFLE_I]], <4 x double> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT:    ret <8 x double> [[SHUFFLE1_I]]
+//
 __m512d test_mm512_castpd128_pd512(__m128d A){
-  // CHECK-LABEL: test_mm512_castpd128_pd512
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castpd128_pd512(A);
 }
 
+// CHECK-LABEL: define dso_local <16 x float> @test_mm512_castps128_ps512(
+// CHECK-SAME: <4 x float> noundef [[A:%.*]]) #[[ATTR1]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[__B_I:%.*]] = alloca <8 x float>, align 32
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    store <4 x float> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x float> [[TMP0]], ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = freeze <8 x float> poison
+// CHECK-NEXT:    store <8 x float> [[TMP1]], ptr [[__B_I]], align 32
+// CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP3:%.*]] = freeze <4 x float> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT:    [[TMP4:%.*]] = load <8 x float>, ptr [[__B_I]], align 32
+// CHECK-NEXT:    [[SHUFFLE1_I:%.*]] = shufflevector <8 x float> [[SHUFFLE_I]], <8 x float> [[TMP4]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+// CHECK-NEXT:    ret <16 x float> [[SHUFFLE1_I]]
+//
 __m512 test_mm512_castps128_ps512(__m128 A){
-  // CHECK-LABEL: test_mm512_castps128_ps512
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castps128_ps512(A);
 }
 
+// CHECK-LABEL: define dso_local <8 x i64> @test_mm512_castsi128_si512(
+// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR1]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    [[__B_I:%.*]] = alloca <4 x i64>, align 32
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
+// CHECK-NEXT:    store <2 x i64> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x i64> [[TMP0]], ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = freeze <4 x i64> poison
+// CHECK-NEXT:    store <4 x i64> [[TMP1]], ptr [[__B_I]], align 32
+// CHECK-NEXT:    [[TMP2:%.*]] = load <2 x i64>, ptr [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP3:%.*]] = freeze <2 x i64> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-NEXT:    [[TMP4:%.*]] = load <4 x i64>, ptr [[__B_I]], align 32
+// CHECK-NEXT:    [[SHUFFLE1_I:%.*]] = shufflevector <4 x i64> [[SHUFFLE_I]], <4 x i64> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT:    ret <8 x i64> [[SHUFFLE1_I]]
+//
 __m512i test_mm512_castsi128_si512(__m128i A){
-  // CHECK-LABEL: test_mm512_castsi128_si512
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castsi128_si512(A);
 }
 
+// CHECK-LABEL: define dso_local <8 x i64> @test_mm512_castsi256_si512(
+// CHECK-SAME: <4 x i64> noundef [[A:%.*]]) #[[ATTR1]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <4 x i64>, align 32
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <4 x i64>, align 32
+// CHECK-NEXT:    store <4 x i64> [[A]], ptr [[A_ADDR]], align 32
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i64>, ptr [[A_ADDR]], align 32
+// CHECK-NEXT:    store <4 x i64> [[TMP0]], ptr [[__A_ADDR_I]], align 32
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i64>, ptr [[__A_ADDR_I]], align 32
+// CHECK-NEXT:    [[TMP2:%.*]] = freeze <4 x i64> poison
+// CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+// CHECK-NEXT:    ret <8 x i64> [[SHUFFLE_I]]
+//
 __m512i test_mm512_castsi256_si512(__m256i A){
-  // CHECK-LABEL: test_mm512_castsi256_si512
-  // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
-  // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castsi256_si512(A);
 }
diff --git a/clang/test/CodeGen/X86/avx-cmp-builtins.c b/clang/test/CodeGen/X86/avx-cmp-builtins.c
index c4e3c7ccd54988..f98cf041c05ea0 100644
--- a/clang/test/CodeGen/X86/avx-cmp-builtins.c
+++ b/clang/test/CodeGen/X86/avx-cmp-builtins.c
@@ -1,5 +1,6 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -O3 -triple=x86_64-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -O3 -triple=i386-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-- -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-X32
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386-- -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-X64
 // FIXME: The shufflevector instructions in test_cmpgt_sd are relying on O3 here.
 
 
@@ -9,62 +10,694 @@
 // Test LLVM IR codegen of cmpXY instructions
 //
 
+// CHECK-LABEL: define dso_local <2 x double> @test_cmp_sd(
+// CHECK-SAME: <2 x double> noundef [[A:%.*]], <2 x double> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[A_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-NEXT:    store <2 x double> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    store <2 x double> [[B]], ptr [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16
+// CHECK-NEXT:    [[TMP1:%.*]] = load <2 x double>, ptr [[B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP2:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP0]], <2 x double> [[TMP1]], i8 13)
+// CHECK-NEXT:    ret <2 x double> [[TMP2]]
+// CHECK-X32-LABEL: define dso_local <2 x double> @test_cmp_sd(
+// CHECK-X32-SAME: <2 x double> noundef [[A:%.*]], <2 x double> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-X32-NEXT:  [[ENTRY:.*:]]
+// CHECK-X32-NEXT:    [[A_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-X32-NEXT:    [[B_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-X32-NEXT:    store <2 x double> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-X32-NEXT:    store <2 x double> [[B]], ptr [[B_ADDR]], align 16
+// CHECK-X32-NEXT:    [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16
+// CHECK-X32-NEXT:    [[TMP1:%.*]] = load <2 x double>, ptr [[B_ADDR]], align 16
+// CHECK-X32-NEXT:    [[TMP2:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP0]], <2 x double> [[TMP1]], i8 13)
+// CHECK-X32-NEXT:    ret <2 x double> [[TMP2]]
+//
+// CHECK-X64-LABEL: define dso_local <2 x double> @test_cmp_sd(
+// CHECK-X64-SAME: <2 x double> noundef [[A:%.*]], <2 x double> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-X64-NEXT:  [[ENTRY:.*:]]
+// CHECK-X64-NEXT:    [[A_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-X64-NEXT:    [[B_ADDR:%.*]] = alloca <2 x double>, align 16
+// CHECK-X64-NEXT:    store <2 x double> [[A]], ptr [[A_ADDR]], align 16
+// CHECK-X64-NEXT:    store <2 x double> [[B]], ptr [[B_ADDR]], align 16
+// CHECK-X64-NEXT:    [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16
+// CHECK-X64-NEXT:    [[TMP1:%.*]] = load <2 x double>, ptr [[B_ADDR]], align 16
+// CHECK-X64-NEXT:    [[TMP2:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP0]], <2 x double> [[TMP1]], i8 13)
+// CHECK-X64-NEXT:    ret <2 x double> [[TMP2]]
+//
 __m128d test_cmp_sd(__m128d a, __m128d b) {
   // Expects that the third argument i...
[truncated]

@MatzeB MatzeB mentioned this pull request Oct 25, 2024
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@MatzeB MatzeB requested a review from yuxuanchen1997 October 25, 2024 20:05
efriedma-quic
efriedma-quic reviewed Oct 25, 2024
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RKSimon
RKSimon approved these changes Oct 28, 2024
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LGTM with minors

efriedma-quic
efriedma-quic approved these changes Oct 28, 2024
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LGTM

@MatzeB MatzeB merged commit 36c1194 into llvm:main Oct 28, 2024
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NoumanAmir657 pushed a commit to NoumanAmir657/llvm-project that referenced this pull request Nov 4, 2024
@MatzeB @NoumanAmir657
Remove optimization flags from clang codegen tests (llvm#113714)
dee4234 
- Remove an -O3 flag from a couple of clang x86 codegen tests so the
  tests do not need to be updated when optimizations in LLVM change.
- Change the tests to use utils/update_cc_test_checks.sh
- Change from apple/darwin triples to generic x86_64-- and
  i386-- because it was not relevant to the test but
  `update_cc_test_checks` seems to be unable to handle platforms that
  prepend `_` to function names.
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