[RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. #113981
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…sent. I received a report that the outliner drops memoperands and causes this code to crash. Handle this by only copying the memoperand if it exists.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesI received a report that the outliner drops memoperands and causes this code to crash. Handle this by only copying the memoperand if it exists. Similar for expandRV32ZdinxLoad Full diff: https://github.com/llvm/llvm-project/pull/113981.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 5dcec078856ead..eb3e1a1fe9fd5e 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -320,34 +320,37 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
Register Hi =
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
- assert(MBBI->hasOneMemOperand() && "Expected mem operand");
- MachineMemOperand *OldMMO = MBBI->memoperands().front();
- MachineFunction *MF = MBB.getParent();
- MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
- MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
-
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
- .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
- .addReg(MBBI->getOperand(1).getReg())
- .add(MBBI->getOperand(2))
- .setMemRefs(MMOLo);
+ auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
+ .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
+ .addReg(MBBI->getOperand(1).getReg())
+ .add(MBBI->getOperand(2));
+ MachineInstrBuilder MIBHi;
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
- .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
- .add(MBBI->getOperand(1))
- .add(MBBI->getOperand(2))
- .setMemRefs(MMOHi);
+ MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
+ .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
+ .add(MBBI->getOperand(1))
+ .add(MBBI->getOperand(2));
} else {
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
- .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
- .add(MBBI->getOperand(1))
- .addImm(MBBI->getOperand(2).getImm() + 4)
- .setMemRefs(MMOHi);
+ MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
+ .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
+ .add(MBBI->getOperand(1))
+ .addImm(MBBI->getOperand(2).getImm() + 4);
+ }
+
+ if (!MBBI->memoperands_empty()) {
+ assert(MBBI->hasOneMemOperand() && "Expected mem operand");
+ MachineMemOperand *OldMMO = MBBI->memoperands().front();
+ MachineFunction *MF = MBB.getParent();
+ MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
+ MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
+ MIBLo.setMemRefs(MMOLo);
+ MIBHi.setMemRefs(MMOHi);
}
+
MBBI->eraseFromParent();
return true;
}
@@ -364,46 +367,48 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
Register Hi =
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
- assert(MBBI->hasOneMemOperand() && "Expected mem operand");
- MachineMemOperand *OldMMO = MBBI->memoperands().front();
- MachineFunction *MF = MBB.getParent();
- MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
- MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
+ MachineInstrBuilder MIBLo, MIBHi;
// If the register of operand 1 is equal to the Lo register, then swap the
// order of loading the Lo and Hi statements.
bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
// Order: Lo, Hi
if (!IsOp1EqualToLo) {
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
- .addReg(MBBI->getOperand(1).getReg())
- .add(MBBI->getOperand(2))
- .setMemRefs(MMOLo);
+ MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
+ .addReg(MBBI->getOperand(1).getReg())
+ .add(MBBI->getOperand(2));
}
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
auto Offset = MBBI->getOperand(2).getOffset();
assert(Offset % 8 == 0);
MBBI->getOperand(2).setOffset(Offset + 4);
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
- .addReg(MBBI->getOperand(1).getReg())
- .add(MBBI->getOperand(2))
- .setMemRefs(MMOHi);
+ MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
+ .addReg(MBBI->getOperand(1).getReg())
+ .add(MBBI->getOperand(2));
MBBI->getOperand(2).setOffset(Offset);
} else {
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
- .addReg(MBBI->getOperand(1).getReg())
- .addImm(MBBI->getOperand(2).getImm() + 4)
- .setMemRefs(MMOHi);
+ MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
+ .addReg(MBBI->getOperand(1).getReg())
+ .addImm(MBBI->getOperand(2).getImm() + 4);
}
// Order: Hi, Lo
if (IsOp1EqualToLo) {
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
- .addReg(MBBI->getOperand(1).getReg())
- .add(MBBI->getOperand(2))
- .setMemRefs(MMOLo);
+ MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
+ .addReg(MBBI->getOperand(1).getReg())
+ .add(MBBI->getOperand(2));
+ }
+
+ if (!MBBI->memoperands_empty()) {
+ assert(MBBI->hasOneMemOperand() && "Expected mem operand");
+ MachineMemOperand *OldMMO = MBBI->memoperands().front();
+ MachineFunction *MF = MBB.getParent();
+ MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
+ MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
+ MIBLo.setMemRefs(MMOLo);
+ MIBHi.setMemRefs(MMOHi);
}
MBBI->eraseFromParent();
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NoumanAmir657
pushed a commit
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that referenced
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Nov 4, 2024
…sent. (llvm#113981) I received a report that the outliner drops memoperands and causes this code to crash. Handle this by only copying the memoperand if it exists. Similar for expandRV32ZdinxLoad
qiaojbao
pushed a commit
to GPUOpen-Drivers/llvm-project
that referenced
this pull request
Dec 4, 2024
…a0708702b Local branch amd-gfx 4eaa070 Merged main:a4fd3dba6e285734bc635b0651a30dfeffedeada into amd-gfx:7dad81725749 Remote branch main 3f4468f [RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. (llvm#113981) Change-Id: I5de1c2e581441dbfb97e34c12805499a88c6bc68
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Hi Craig, the issue is still there with the following MIR: Regards, |
Do you have test that generates that MIR? I'm not sure where in the code 2 operands can be created. |
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Hi, Sorry for the late answer, I created a reduced test: https://godbolt.org/z/sPs4E16x6 Regards, Gergely This is the relevant part: |
Should be fixed after d4af658 |
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I received a report that the outliner drops memoperands and causes this code to crash. Handle this by only copying the memoperand if it exists.
Similar for expandRV32ZdinxLoad