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[AArch64] Add assembly/disassembly for zeroing SVE REV{B,H,W,D} and RBIT #114110

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Oct 31, 2024
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[AArch64] Add assembly/disassembly for zeroing SVE REV{B,H,W,D} and RBIT #114110

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[AArch64] Add assembly/disassembly for zeroing SVE REV{B,H,W,D} and RBIT
SpencerAbson Oct 29, 2024
6134823
Remove redundant revd class and revw multiclass
SpencerAbson Oct 31, 2024
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7 changes: 7 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Expand Up @@ -4307,6 +4307,13 @@ let Predicates = [HasSVE2p2orSME2p2] in {
// SVE predicate count
defm FIRSTP_XPP : sve_int_pcount_pred_tmp<0b001, "firstp">;
defm LASTP_XPP : sve_int_pcount_pred_tmp<0b010, "lastp">;

// SVE reverse within elements, zeroing predicate
defm RBIT_ZPzZ : sve_int_perm_rev_rbit_z<"rbit">;
defm REVB_ZPzZ : sve_int_perm_rev_revb_z<"revb">;
defm REVH_ZPzZ : sve_int_perm_rev_revh_z<"revh">;
def REVW_ZPzZ : sve_int_perm_rev_z<0b11, 0b0110, "revw", ZPR64>;
def REVD_ZPzZ : sve_int_perm_rev_z<0b00, 0b1110, "revd", ZPR128>;
} // End HasSME2p2orSVE2p2

//===----------------------------------------------------------------------===//
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39 changes: 39 additions & 0 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -7429,6 +7429,45 @@ multiclass sve_int_perm_rev_revw<string asm, SDPatternOperator op> {
def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
}

class sve_int_perm_rev_z<bits<2> sz, bits<4> opc, string asm,
ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
asm, "\t$Zd, $Pg/z, $Zn",
"",
[]>, Sched<[]> {
bits<5> Zd;
bits<3> Pg;
bits<5> Zn;
let Inst{31-24} = 0b00000101;
let Inst{23-22} = sz;
let Inst{21-20} = 0b10;
let Inst{19-16} = opc;
let Inst{15-13} = 0b101;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;

let hasSideEffects = 0;
}

multiclass sve_int_perm_rev_rbit_z<string asm> {
def _B : sve_int_perm_rev_z<0b00, 0b0111, asm, ZPR8>;
def _H : sve_int_perm_rev_z<0b01, 0b0111, asm, ZPR16>;
def _S : sve_int_perm_rev_z<0b10, 0b0111, asm, ZPR32>;
def _D : sve_int_perm_rev_z<0b11, 0b0111, asm, ZPR64>;
}

multiclass sve_int_perm_rev_revb_z<string asm> {
def _H : sve_int_perm_rev_z<0b01, 0b0100, asm, ZPR16>;
def _S : sve_int_perm_rev_z<0b10, 0b0100, asm, ZPR32>;
def _D : sve_int_perm_rev_z<0b11, 0b0100, asm, ZPR64>;
}

multiclass sve_int_perm_rev_revh_z<string asm> {
def _S : sve_int_perm_rev_z<0b10, 0b0101, asm, ZPR32>;
def _D : sve_int_perm_rev_z<0b11, 0b0101, asm, ZPR64>;
}

class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
RegisterClass srcRegType>
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),
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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SME/revd-diagnostics.s
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Expand Up @@ -11,7 +11,7 @@ revd z0.q, p8/m, z0.q

// wrong predication qualifier, expected /m.
revd z0.q, p0/z, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
// CHECK-NEXT: revd z0.q, p0/z, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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74 changes: 74 additions & 0 deletions llvm/test/MC/AArch64/SVE2p2/rbit_z-diagnostics.s
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/ RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s

// ------------------------------------------------------------------------- //
// Invalid predicate

rbit z0.b, p8/z, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: rbit z0.b, p8/z, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

rbit z0.h, p8/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: rbit z0.h, p8/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

rbit z0.s, p8/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: rbit z0.s, p8/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

rbit z0.d, p8/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: rbit z0.d, p8/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid element widths

rbit z0.b, p7/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rbit z0.b, p7/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

rbit z0.h, p7/z, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rbit z0.h, p7/z, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

rbit z0.s, p7/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rbit z0.s, p7/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

rbit z0.d, p7/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: rbit z0.d, p7/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx

movprfx z0.b, p0/z, z7.b
rbit z0.b, p0/z, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rbit z0.b, p0/z, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movprfx z0, z7
rbit z0.h, p0/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rbit z0.h, p0/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movprfx z0.s, p0/z, z7.s
rbit z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rbit z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movprfx z0, z7
rbit z0.d, p0/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: rbit z0.d, p0/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
45 changes: 45 additions & 0 deletions llvm/test/MC/AArch64/SVE2p2/rbit_z.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

rbit z0.b, p0/z, z0.b // 00000101-00100111-10100000-00000000
// CHECK-INST: rbit z0.b, p0/z, z0.b
// CHECK-ENCODING: [0x00,0xa0,0x27,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 0527a000 <unknown>

rbit z21.b, p5/z, z10.b // 00000101-00100111-10110101-01010101
// CHECK-INST: rbit z21.b, p5/z, z10.b
// CHECK-ENCODING: [0x55,0xb5,0x27,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 0527b555 <unknown>

rbit z23.h, p3/z, z13.h // 00000101-01100111-10101101-10110111
// CHECK-INST: rbit z23.h, p3/z, z13.h
// CHECK-ENCODING: [0xb7,0xad,0x67,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 0567adb7 <unknown>

rbit z23.s, p3/z, z13.s // 00000101-10100111-10101101-10110111
// CHECK-INST: rbit z23.s, p3/z, z13.s
// CHECK-ENCODING: [0xb7,0xad,0xa7,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 05a7adb7 <unknown>

rbit z31.d, p7/z, z31.d // 00000101-11100111-10111111-11111111
// CHECK-INST: rbit z31.d, p7/z, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xe7,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 05e7bfff <unknown>
63 changes: 63 additions & 0 deletions llvm/test/MC/AArch64/SVE2p2/revb_z-diagnostics.s
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s

// ------------------------------------------------------------------------- //
// Invalid predicate

revb z0.h, p8/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: revb z0.h, p8/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revb z0.s, p8/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: revb z0.s, p8/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revb z0.d, p8/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: revb z0.d, p8/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid element widths

revb z0.b, p7/z, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revb z0.b, p7/z, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revb z0.h, p7/z, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revb z0.h, p7/z, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revb z0.s, p7/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revb z0.s, p7/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revb z0.d, p7/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revb z0.d, p7/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx

movprfx z0, z7
revb z0.h, p0/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: revb z0.h, p0/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movprfx z0.s, p0/z, z7.s
revb z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: revb z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movprfx z0, z7
revb z0.d, p0/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: revb z0.d, p0/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33 changes: 33 additions & 0 deletions llvm/test/MC/AArch64/SVE2p2/revb_z.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

revb z0.h, p0/z, z0.h // 00000101-01100100-10100000-00000000
// CHECK-INST: revb z0.h, p0/z, z0.h
// CHECK-ENCODING: [0x00,0xa0,0x64,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 0564a000 <unknown>

revb z23.s, p3/z, z13.s // 00000101-10100100-10101101-10110111
// CHECK-INST: revb z23.s, p3/z, z13.s
// CHECK-ENCODING: [0xb7,0xad,0xa4,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 05a4adb7 <unknown>

revb z31.d, p7/z, z31.d // 00000101-11100100-10111111-11111111
// CHECK-INST: revb z31.d, p7/z, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xe4,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 05e4bfff <unknown>
56 changes: 56 additions & 0 deletions llvm/test/MC/AArch64/SVE2p2/revd_z-diagnostics.s
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s

// ------------------------------------------------------------------------- //
// Invalid predicate

revd z0.q, p8/z, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: revd z0.q, p8/z, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid element widths

revd z0.b, p7/z, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revd z0.b, p7/z, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revd z0.h, p7/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revd z0.h, p7/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revd z0.s, p7/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revd z0.s, p7/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revd z0.h, p7/z, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revd z0.h, p7/z, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revd z0.s, p7/z, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revd z0.s, p7/z, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revd z0.d, p7/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revd z0.d, p7/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

revd z0.q, p7/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revd z0.q, p7/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx

movprfx z0, z7
revd z0.q, p0/z, z0.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: revd z0.q, p0/z, z0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33 changes: 33 additions & 0 deletions llvm/test/MC/AArch64/SVE2p2/revd_z.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

revd z0.q, p0/z, z0.q // 00000101-00101110-10100000-00000000
// CHECK-INST: revd z0.q, p0/z, z0.q
// CHECK-ENCODING: [0x00,0xa0,0x2e,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 052ea000 <unknown>

revd z23.q, p3/z, z13.q // 00000101-00101110-10101101-10110111
// CHECK-INST: revd z23.q, p3/z, z13.q
// CHECK-ENCODING: [0xb7,0xad,0x2e,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 052eadb7 <unknown>

revd z31.q, p7/z, z31.q // 00000101-00101110-10111111-11111111
// CHECK-INST: revd z31.q, p7/z, z31.q
// CHECK-ENCODING: [0xff,0xbf,0x2e,0x05]
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
// CHECK-UNKNOWN: 052ebfff <unknown>
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