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[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits #114389

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Merged
merged 1 commit into from
Oct 31, 2024
Merged

[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits #114389

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18 changes: 18 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -808,6 +808,24 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
}
break;
}
case ISD::SRL: {
// If we are only demanding sign bits then we can use the shift source
// directly.
if (std::optional<uint64_t> MaxSA =
DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
SDValue Op0 = Op.getOperand(0);
unsigned ShAmt = *MaxSA;
// Must already be signbits in DemandedBits bounds, and can't demand any
// shifted in zeroes.
if (DemandedBits.countl_zero() >= ShAmt) {
unsigned NumSignBits =
DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
if (DemandedBits.countr_zero() >= (BitWidth - NumSignBits))
return Op0;
}
}
break;
}
case ISD::SETCC: {
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
Expand Down
50 changes: 22 additions & 28 deletions llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1052,16 +1052,15 @@ define noundef i64 @srem64_i32max(i64 noundef %i) {
; GFX9-NEXT: s_mov_b32 s6, 0x80000001
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, 3, v[2:3]
; GFX9-NEXT: v_mul_i32_i24_e32 v8, 3, v6
; GFX9-NEXT: v_lshl_add_u32 v9, v6, 31, v6
; GFX9-NEXT: v_mov_b32_e32 v10, v5
; GFX9-NEXT: v_lshl_add_u32 v8, v6, 31, v6
; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, 3, 0
; GFX9-NEXT: v_mov_b32_e32 v9, v5
; GFX9-NEXT: v_mov_b32_e32 v5, v3
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[4:5]
; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, 3, 0
; GFX9-NEXT: v_mov_b32_e32 v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2
; GFX9-NEXT: v_add3_u32 v7, v7, v9, v8
; GFX9-NEXT: v_add3_u32 v7, v7, v8, v6
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, -1, v[6:7]
; GFX9-NEXT: v_mov_b32_e32 v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v9, v2
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s6, v[2:3]
; GFX9-NEXT: v_sub_u32_e32 v5, v5, v1
Expand All @@ -1085,10 +1084,9 @@ define noundef i64 @srem64_i32max(i64 noundef %i) {
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX942-NEXT: v_mul_i32_i24_e32 v4, 3, v2
; GFX942-NEXT: v_lshl_add_u32 v5, v2, 31, v2
; GFX942-NEXT: v_lshl_add_u32 v4, v2, 31, v2
; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, 0
; GFX942-NEXT: v_add3_u32 v3, v3, v5, v4
; GFX942-NEXT: v_add3_u32 v3, v3, v4, v2
; GFX942-NEXT: v_mul_hi_u32 v4, v0, 3
; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v1, 3, v[4:5]
Expand Down Expand Up @@ -1125,17 +1123,16 @@ define noundef i64 @srem64_i32max(i64 noundef %i) {
; GFX1030-NEXT: v_mul_hi_u32 v2, v0, 3
; GFX1030-NEXT: v_mov_b32_e32 v3, 0
; GFX1030-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX1030-NEXT: v_mul_i32_i24_e32 v7, 3, v6
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, 3, v[2:3]
; GFX1030-NEXT: v_mov_b32_e32 v8, v5
; GFX1030-NEXT: v_mov_b32_e32 v7, v5
; GFX1030-NEXT: v_mov_b32_e32 v5, v3
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v6, 3, 0
; GFX1030-NEXT: v_lshl_add_u32 v6, v6, 31, v6
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x80000001, v0, v[4:5]
; GFX1030-NEXT: v_add3_u32 v3, v3, v6, v7
; GFX1030-NEXT: v_add3_u32 v3, v3, v6, v2
; GFX1030-NEXT: v_mov_b32_e32 v4, v5
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, -1, v[2:3]
; GFX1030-NEXT: v_add_co_u32 v4, s4, v8, v4
; GFX1030-NEXT: v_add_co_u32 v4, s4, v7, v4
; GFX1030-NEXT: v_add_co_ci_u32_e64 v5, null, 0, 0, s4
; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v3, v1
; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x80000001, v1, v[4:5]
Expand Down Expand Up @@ -1167,16 +1164,15 @@ define noundef i64 @sdiv64_i32max(i64 noundef %i) {
; GFX9-NEXT: s_mov_b32 s6, 0x80000001
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, 3, v[2:3]
; GFX9-NEXT: v_mul_i32_i24_e32 v8, 3, v6
; GFX9-NEXT: v_lshl_add_u32 v9, v6, 31, v6
; GFX9-NEXT: v_mov_b32_e32 v10, v5
; GFX9-NEXT: v_lshl_add_u32 v8, v6, 31, v6
; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, 3, 0
; GFX9-NEXT: v_mov_b32_e32 v9, v5
; GFX9-NEXT: v_mov_b32_e32 v5, v3
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[4:5]
; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, 3, 0
; GFX9-NEXT: v_mov_b32_e32 v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v10, v2
; GFX9-NEXT: v_add3_u32 v7, v7, v9, v8
; GFX9-NEXT: v_add3_u32 v7, v7, v8, v6
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, -1, v[6:7]
; GFX9-NEXT: v_mov_b32_e32 v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v9, v2
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s6, v[2:3]
; GFX9-NEXT: v_sub_u32_e32 v5, v5, v1
Expand All @@ -1195,10 +1191,9 @@ define noundef i64 @sdiv64_i32max(i64 noundef %i) {
; GFX942: ; %bb.0: ; %entry
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX942-NEXT: v_mul_i32_i24_e32 v4, 3, v2
; GFX942-NEXT: v_lshl_add_u32 v5, v2, 31, v2
; GFX942-NEXT: v_lshl_add_u32 v4, v2, 31, v2
; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, 0
; GFX942-NEXT: v_add3_u32 v3, v3, v5, v4
; GFX942-NEXT: v_add3_u32 v3, v3, v4, v2
; GFX942-NEXT: v_mul_hi_u32 v4, v0, 3
; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: v_mad_u64_u32 v[6:7], s[0:1], v1, 3, v[4:5]
Expand Down Expand Up @@ -1227,17 +1222,16 @@ define noundef i64 @sdiv64_i32max(i64 noundef %i) {
; GFX1030-NEXT: v_mul_hi_u32 v2, v0, 3
; GFX1030-NEXT: v_mov_b32_e32 v3, 0
; GFX1030-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX1030-NEXT: v_mul_i32_i24_e32 v7, 3, v6
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, v1, 3, v[2:3]
; GFX1030-NEXT: v_mov_b32_e32 v8, v5
; GFX1030-NEXT: v_mov_b32_e32 v7, v5
; GFX1030-NEXT: v_mov_b32_e32 v5, v3
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v6, 3, 0
; GFX1030-NEXT: v_lshl_add_u32 v6, v6, 31, v6
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x80000001, v0, v[4:5]
; GFX1030-NEXT: v_add3_u32 v3, v3, v6, v7
; GFX1030-NEXT: v_add3_u32 v3, v3, v6, v2
; GFX1030-NEXT: v_mov_b32_e32 v4, v5
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v0, -1, v[2:3]
; GFX1030-NEXT: v_add_co_u32 v4, s4, v8, v4
; GFX1030-NEXT: v_add_co_u32 v4, s4, v7, v4
; GFX1030-NEXT: v_add_co_ci_u32_e64 v5, null, 0, 0, s4
; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v3, v1
; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, 0x80000001, v1, v[4:5]
Expand Down
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