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[AArch64] make REVD non-MOVPRFXable #114430

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Merged
merged 1 commit into from
Nov 5, 2024
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[AArch64] make REVD non-MOVPRFXable #114430

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2 changes: 0 additions & 2 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1429,8 +1429,6 @@ class sve2_int_perm_revd<string asm>
let Inst{4-0} = Zd;

let Constraints = "$Zd = $_Zd";
let DestructiveInstType = DestructiveUnary;
let ElementSize = ZPR128.ElementSize;
}

multiclass sve2_int_perm_revd<string asm, SDPatternOperator op> {
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9 changes: 9 additions & 0 deletions llvm/test/MC/AArch64/SME/revd-diagnostics.s
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Expand Up @@ -27,3 +27,12 @@ revd z0.q, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: revd z0.q, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx

movprfx z21, z25
revd z21.q, p5/m, z10.q
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: revd z21.q, p5/m, z10.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
17 changes: 1 addition & 16 deletions llvm/test/MC/AArch64/SME/revd.s
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Expand Up @@ -34,19 +34,4 @@ revd z31.q, p7/m, z31.q
// CHECK-INST: revd z31.q, p7/m, z31.q
// CHECK-ENCODING: [0xff,0x9f,0x2e,0x05]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 052e9fff <unknown>

// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.

movprfx z21, z25
// CHECK-INST: movprfx z21, z25
// CHECK-ENCODING: [0x35,0xbf,0x20,0x04]
// CHECK-ERROR: instruction requires: sve or sme
// CHECK-UNKNOWN: 0420bf35 <unknown>

revd z21.q, p5/m, z10.q
// CHECK-INST: revd z21.q, p5/m, z10.q
// CHECK-ENCODING: [0x55,0x95,0x2e,0x05]
// CHECK-ERROR: instruction requires: sme
// CHECK-UNKNOWN: 052e9555 <unknown>
// CHECK-UNKNOWN: 052e9fff <unknown>
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