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[ARM] Fix CMSE S->NS calls when CONTROL_S.SFPA==0 (CVE-2024-7883) #114433

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Merged
merged 4 commits into from
Nov 1, 2024
Merged

[ARM] Fix CMSE S->NS calls when CONTROL_S.SFPA==0 (CVE-2024-7883) #114433

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9b6e64c
Re-generate test for changed assembly syntax
ostannard Aug 1, 2024
04061b1
[ARM] Fix CMSE S->NS calls when CONTROL_S.SFPA==0 (CVE-2024-7883)
ostannard Aug 1, 2024
573ca88
Merge remote-tracking branch 'origin/main' into cmse-sfpa
ostannard Nov 1, 2024
54150ed
Add tests with undef/poison arguments
ostannard Nov 1, 2024
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44 changes: 41 additions & 3 deletions llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1426,6 +1426,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
// Use ScratchRegs to store the fp regs
std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
std::vector<unsigned> NonclearedFPRegs;
bool ReturnsFPReg = false;
for (const MachineOperand &Op : MBBI->operands()) {
if (Op.isReg() && Op.isUse()) {
Register Reg = Op.getReg();
Expand Down Expand Up @@ -1460,14 +1461,51 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
NonclearedFPRegs.push_back(Reg);
}
}
} else if (Op.isReg() && Op.isDef()) {
Register Reg = Op.getReg();
if (ARM::SPRRegClass.contains(Reg) || ARM::DPRRegClass.contains(Reg) ||
ARM::QPRRegClass.contains(Reg))
ReturnsFPReg = true;
}
}

bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
bool PassesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());

if (passesFPReg)
if (PassesFPReg || ReturnsFPReg)
assert(STI->hasFPRegs() && "Subtarget needs fpregs");

// CVE-2024-7883
//
// The VLLDM/VLSTM instructions set up lazy state preservation, but they
// execute as NOPs if the FP register file is not considered to contain
// secure data, represented by the CONTROL_S.SFPA bit. This means that the
// state of CONTROL_S.SFPA must be the same when these two instructions are
// executed. That might not be the case if we haven't used any FP
// instructions before the VLSTM, so CONTROL_S.SFPA is clear, but do have one
// before the VLLDM, which sets it..
//
// If we can't prove that SFPA will be the same for the VLSTM and VLLDM, we
// execute a "vmov s0, s0" instruction before the VLSTM to ensure that
// CONTROL_S.SFPA is set for both.
//
// That can only happen for callees which take no FP arguments (or we'd have
// inserted a VMOV above) and which return values in FP regs (so that we need
// to use a VMOV to back-up the return value before the VLLDM). It also can't
// happen if the call is dominated by other existing floating-point
// instructions, but we don't currently check for that case.
//
// These conditions mean that we only emit this instruction when using the
// hard-float ABI, which means we can assume that FP instructions are
// available, and don't need to make it conditional like we do for the
// CVE-2021-35465 workaround.
if (ReturnsFPReg && !PassesFPReg) {
bool S0Dead = !LiveRegs.contains(ARM::S0);
BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVS))
.addReg(ARM::S0, RegState::Define | getDeadRegState(S0Dead))
.addReg(ARM::S0, getUndefRegState(S0Dead))
.add(predOps(ARMCC::AL));
}

// Lazy store all fp registers to the stack.
// This executes as NOP in the absence of floating-point support.
MachineInstrBuilder VLSTM =
Expand Down Expand Up @@ -1528,7 +1566,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
}
// restore FPSCR from stack and clear bits 0-4, 7, 28-31
// The other bits are program global according to the AAPCS
if (passesFPReg) {
if (PassesFPReg) {
BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg)
.addReg(ARM::SP)
.addImm(0x10)
Expand Down
63 changes: 33 additions & 30 deletions llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -187,7 +187,7 @@ define float @f2(ptr nocapture %fptr) #2 {
; CHECK-8M-NEXT: bic r0, r0, #1
; CHECK-8M-NEXT: sub sp, #136
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: ldr r1, [sp, #64]
; CHECK-8M-NEXT: bic r1, r1, #159
Expand All @@ -207,7 +207,7 @@ define float @f2(ptr nocapture %fptr) #2 {
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -245,7 +245,7 @@ define double @d2(ptr nocapture %fptr) #2 {
; CHECK-8M-LE-NEXT: bic r0, r0, #1
; CHECK-8M-LE-NEXT: sub sp, #136
; CHECK-8M-LE-NEXT: vmov r11, r12, d0
; CHECK-8M-LE-NEXT: vlstm sp
; CHECK-8M-LE-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-LE-NEXT: vmov d0, r11, r12
; CHECK-8M-LE-NEXT: ldr r1, [sp, #64]
; CHECK-8M-LE-NEXT: bic r1, r1, #159
Expand All @@ -264,7 +264,7 @@ define double @d2(ptr nocapture %fptr) #2 {
; CHECK-8M-LE-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-LE-NEXT: blxns r0
; CHECK-8M-LE-NEXT: vmov r11, r12, d0
; CHECK-8M-LE-NEXT: vlldm sp
; CHECK-8M-LE-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-LE-NEXT: vmov d0, r11, r12
; CHECK-8M-LE-NEXT: add sp, #136
; CHECK-8M-LE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand All @@ -283,7 +283,7 @@ define double @d2(ptr nocapture %fptr) #2 {
; CHECK-8M-BE-NEXT: bic r0, r0, #1
; CHECK-8M-BE-NEXT: sub sp, #136
; CHECK-8M-BE-NEXT: vmov r11, r12, d0
; CHECK-8M-BE-NEXT: vlstm sp
; CHECK-8M-BE-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-BE-NEXT: vmov d0, r11, r12
; CHECK-8M-BE-NEXT: ldr r1, [sp, #64]
; CHECK-8M-BE-NEXT: bic r1, r1, #159
Expand All @@ -302,7 +302,7 @@ define double @d2(ptr nocapture %fptr) #2 {
; CHECK-8M-BE-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-BE-NEXT: blxns r0
; CHECK-8M-BE-NEXT: vmov r11, r12, d0
; CHECK-8M-BE-NEXT: vlldm sp
; CHECK-8M-BE-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-BE-NEXT: vmov d0, r11, r12
; CHECK-8M-BE-NEXT: add sp, #136
; CHECK-8M-BE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -368,7 +368,7 @@ define float @f3(ptr nocapture %fptr) #4 {
; CHECK-8M-NEXT: bic r0, r0, #1
; CHECK-8M-NEXT: sub sp, #136
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: ldr r1, [sp, #64]
; CHECK-8M-NEXT: bic r1, r1, #159
Expand All @@ -388,7 +388,7 @@ define float @f3(ptr nocapture %fptr) #4 {
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -426,7 +426,7 @@ define double @d3(ptr nocapture %fptr) #4 {
; CHECK-8M-LE-NEXT: bic r0, r0, #1
; CHECK-8M-LE-NEXT: sub sp, #136
; CHECK-8M-LE-NEXT: vmov r11, r12, d0
; CHECK-8M-LE-NEXT: vlstm sp
; CHECK-8M-LE-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-LE-NEXT: vmov d0, r11, r12
; CHECK-8M-LE-NEXT: ldr r1, [sp, #64]
; CHECK-8M-LE-NEXT: bic r1, r1, #159
Expand All @@ -445,7 +445,7 @@ define double @d3(ptr nocapture %fptr) #4 {
; CHECK-8M-LE-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-LE-NEXT: blxns r0
; CHECK-8M-LE-NEXT: vmov r11, r12, d0
; CHECK-8M-LE-NEXT: vlldm sp
; CHECK-8M-LE-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-LE-NEXT: vmov d0, r11, r12
; CHECK-8M-LE-NEXT: add sp, #136
; CHECK-8M-LE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand All @@ -464,7 +464,7 @@ define double @d3(ptr nocapture %fptr) #4 {
; CHECK-8M-BE-NEXT: bic r0, r0, #1
; CHECK-8M-BE-NEXT: sub sp, #136
; CHECK-8M-BE-NEXT: vmov r11, r12, d0
; CHECK-8M-BE-NEXT: vlstm sp
; CHECK-8M-BE-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-BE-NEXT: vmov d0, r11, r12
; CHECK-8M-BE-NEXT: ldr r1, [sp, #64]
; CHECK-8M-BE-NEXT: bic r1, r1, #159
Expand All @@ -483,7 +483,7 @@ define double @d3(ptr nocapture %fptr) #4 {
; CHECK-8M-BE-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-BE-NEXT: blxns r0
; CHECK-8M-BE-NEXT: vmov r11, r12, d0
; CHECK-8M-BE-NEXT: vlldm sp
; CHECK-8M-BE-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-BE-NEXT: vmov d0, r11, r12
; CHECK-8M-BE-NEXT: add sp, #136
; CHECK-8M-BE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -547,8 +547,9 @@ define float @f4(ptr nocapture %fptr) #6 {
; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
; CHECK-8M-NEXT: bic r0, r0, #1
; CHECK-8M-NEXT: sub sp, #136
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vmov.f32 s0, s0
; CHECK-8M-NEXT: mov r1, r0
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: mov r2, r0
; CHECK-8M-NEXT: mov r3, r0
; CHECK-8M-NEXT: mov r4, r0
Expand All @@ -563,7 +564,7 @@ define float @f4(ptr nocapture %fptr) #6 {
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -598,8 +599,9 @@ define double @d4(ptr nocapture %fptr) #6 {
; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
; CHECK-8M-NEXT: bic r0, r0, #1
; CHECK-8M-NEXT: sub sp, #136
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vmov.f32 s0, s0
; CHECK-8M-NEXT: mov r1, r0
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: mov r2, r0
; CHECK-8M-NEXT: mov r3, r0
; CHECK-8M-NEXT: mov r4, r0
Expand All @@ -614,7 +616,7 @@ define double @d4(ptr nocapture %fptr) #6 {
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vmov r11, r12, d0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov d0, r11, r12
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -649,7 +651,7 @@ define void @fd(ptr %f, float %a, double %b) #8 {
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: mov r2, r0
; CHECK-8M-NEXT: vmov r10, r11, d1
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: vmov d1, r10, r11
; CHECK-8M-NEXT: ldr r1, [sp, #64]
Expand All @@ -666,7 +668,7 @@ define void @fd(ptr %f, float %a, double %b) #8 {
; CHECK-8M-NEXT: mov r9, r0
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
; CHECK-8M-NEXT: pop {r7, pc}
Expand Down Expand Up @@ -708,7 +710,7 @@ define void @fdff(ptr %f, float %a, double %b, float %c, float %d) #8 {
; CHECK-8M-NEXT: vmov r9, s1
; CHECK-8M-NEXT: mov r4, r0
; CHECK-8M-NEXT: vmov r8, s4
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: vmov d1, r10, r11
; CHECK-8M-NEXT: vmov s1, r9
Expand All @@ -723,7 +725,7 @@ define void @fdff(ptr %f, float %a, double %b, float %c, float %d) #8 {
; CHECK-8M-NEXT: mov r7, r0
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
; CHECK-8M-NEXT: pop {r7, pc}
Expand Down Expand Up @@ -765,7 +767,7 @@ define void @fidififid(ptr %fu, float %a, i32 %b, double %c, i32 %d, float %e, i
; CHECK-8M-NEXT: vmov r8, s1
; CHECK-8M-NEXT: vmov r7, s4
; CHECK-8M-NEXT: vmov r5, r6, d3
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r11
; CHECK-8M-NEXT: vmov d1, r9, r10
; CHECK-8M-NEXT: vmov s1, r8
Expand All @@ -778,7 +780,7 @@ define void @fidififid(ptr %fu, float %a, i32 %b, double %c, i32 %d, float %e, i
; CHECK-8M-NEXT: mov r4, r12
; CHECK-8M-NEXT: msr apsr_nzcvqg, r12
; CHECK-8M-NEXT: blxns r12
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
; CHECK-8M-NEXT: pop {r7, pc}
Expand Down Expand Up @@ -897,7 +899,7 @@ define half @h2(ptr nocapture %hptr) nounwind {
; CHECK-8M-NEXT: bic r0, r0, #1
; CHECK-8M-NEXT: sub sp, #136
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: ldr r1, [sp, #64]
; CHECK-8M-NEXT: bic r1, r1, #159
Expand All @@ -917,7 +919,7 @@ define half @h2(ptr nocapture %hptr) nounwind {
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -976,7 +978,7 @@ define half @h3(ptr nocapture %hptr) nounwind {
; CHECK-8M-NEXT: bic r0, r0, #1
; CHECK-8M-NEXT: sub sp, #136
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: ldr r1, [sp, #64]
; CHECK-8M-NEXT: bic r1, r1, #159
Expand All @@ -996,7 +998,7 @@ define half @h3(ptr nocapture %hptr) nounwind {
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -1053,8 +1055,9 @@ define half @h4(ptr nocapture %hptr) nounwind {
; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
; CHECK-8M-NEXT: bic r0, r0, #1
; CHECK-8M-NEXT: sub sp, #136
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vmov.f32 s0, s0
; CHECK-8M-NEXT: mov r1, r0
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: mov r2, r0
; CHECK-8M-NEXT: mov r3, r0
; CHECK-8M-NEXT: mov r4, r0
Expand All @@ -1069,7 +1072,7 @@ define half @h4(ptr nocapture %hptr) nounwind {
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down Expand Up @@ -1176,7 +1179,7 @@ define half @h1_arg(ptr nocapture %hptr, half %harg) nounwind {
; CHECK-8M-NEXT: bic r0, r0, #1
; CHECK-8M-NEXT: sub sp, #136
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlstm sp
; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: ldr r1, [sp, #64]
; CHECK-8M-NEXT: bic r1, r1, #159
Expand All @@ -1196,7 +1199,7 @@ define half @h1_arg(ptr nocapture %hptr, half %harg) nounwind {
; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
; CHECK-8M-NEXT: blxns r0
; CHECK-8M-NEXT: vmov r12, s0
; CHECK-8M-NEXT: vlldm sp
; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
; CHECK-8M-NEXT: vmov s0, r12
; CHECK-8M-NEXT: add sp, #136
; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,7 @@ body: |
# CHECK: $sp = t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, $r4, $r5, $r6, undef $r7, $r8, $r9, $r10, $r11
# CHECK-NEXT: $r0 = t2BICri $r0, 1, 14 /* CC::al */, $noreg, $noreg
# CHECK-NEXT: $sp = tSUBspi $sp, 34, 14 /* CC::al */, $noreg
# CHECK-NEXT: dead $s0 = VMOVS undef $s0, 14 /* CC::al */, $noreg
# CHECK-NEXT: VLSTM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $d0, implicit undef $d1, implicit undef $d2, implicit undef $d3, implicit undef $d4, implicit undef $d5, implicit undef $d6, implicit undef $d7, implicit $d8, implicit $d9, implicit $d10, implicit $d11, implicit $d12, implicit $d13, implicit $d14, implicit $d15
# CHECK-NEXT: $r1 = tMOVr $r0, 14 /* CC::al */, $noreg
# CHECK-NEXT: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
Expand Down
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