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[LoongArch][NFC] Fix the operand constraint of AMCAS instructions #114508

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Merged
merged 1 commit into from
Nov 19, 2024
Merged

[LoongArch][NFC] Fix the operand constraint of AMCAS instructions #114508

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8 changes: 7 additions & 1 deletion llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1562,7 +1562,13 @@ unsigned LoongArchAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
unsigned Opc = Inst.getOpcode();
switch (Opc) {
default:
if (Opc >= LoongArch::AMADD_D && Opc <= LoongArch::AMXOR_W) {
if (Opc >= LoongArch::AMCAS_B && Opc <= LoongArch::AMCAS__DB_W) {
MCRegister Rd = Inst.getOperand(0).getReg();
MCRegister Rk = Inst.getOperand(2).getReg();
MCRegister Rj = Inst.getOperand(3).getReg();
if ((Rd == Rk || Rd == Rj) && Rd != LoongArch::R0)
return Match_RequiresAMORdDifferRkRj;
} else if (Opc >= LoongArch::AMADD_D && Opc <= LoongArch::AMXOR_W) {
MCRegister Rd = Inst.getOperand(0).getReg();
MCRegister Rk = Inst.getOperand(1).getReg();
MCRegister Rj = Inst.getOperand(2).getReg();
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26 changes: 16 additions & 10 deletions llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -710,11 +710,17 @@ class STORE_2RI14<bits<32> op>
"$rd, $rj, $imm14">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1

let hasSideEffects = 0, mayLoad = 1, mayStore = 1, Constraints = "@earlyclobber $rd" in
class AM_3R<bits<32> op>
let hasSideEffects = 0, mayLoad = 1, mayStore = 1,
Constraints = "@earlyclobber $rd" in class AM_3R<bits<32> op>
: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rk, GPRMemAtomic:$rj),
"$rd, $rk, $rj">;

let hasSideEffects = 0, mayLoad = 1, mayStore = 1,
Constraints =
"@earlyclobber $rd_wb, $rd_wb = $rd" in class AMCAS_3R<bits<32> op>
: Fmt3R<op, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rk, GPRMemAtomic:$rj),
"$rd, $rk, $rj">;

let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
class LLBase<bits<32> op>
: Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14),
Expand Down Expand Up @@ -1024,14 +1030,14 @@ def AMMAX__DB_WU : AM_3R<0x38700000>;
def AMMAX__DB_DU : AM_3R<0x38708000>;
def AMMIN__DB_WU : AM_3R<0x38710000>;
def AMMIN__DB_DU : AM_3R<0x38718000>;
def AMCAS_B : AM_3R<0x38580000>;
def AMCAS_H : AM_3R<0x38588000>;
def AMCAS_W : AM_3R<0x38590000>;
def AMCAS_D : AM_3R<0x38598000>;
def AMCAS__DB_B : AM_3R<0x385a0000>;
def AMCAS__DB_H : AM_3R<0x385a8000>;
def AMCAS__DB_W : AM_3R<0x385b0000>;
def AMCAS__DB_D : AM_3R<0x385b8000>;
def AMCAS_B : AMCAS_3R<0x38580000>;
def AMCAS_H : AMCAS_3R<0x38588000>;
def AMCAS_W : AMCAS_3R<0x38590000>;
def AMCAS_D : AMCAS_3R<0x38598000>;
def AMCAS__DB_B : AMCAS_3R<0x385a0000>;
def AMCAS__DB_H : AMCAS_3R<0x385a8000>;
def AMCAS__DB_W : AMCAS_3R<0x385b0000>;
def AMCAS__DB_D : AMCAS_3R<0x385b8000>;
def LL_D : LLBase<0x22000000>;
def SC_D : SCBase<0x23000000>;
def SC_Q : SCBase_128<0x38570000>;
Expand Down
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