[X86][AMX] Move TPAIRS into PositionOrder 3, NFCI #114642
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Should solve compile time regression.
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@llvm/pr-subscribers-backend-x86 Author: Phoebe Wang (phoebewang) ChangesShould solve compile time regression. Full diff: https://github.com/llvm/llvm-project/pull/114642.diff 1 Files Affected:
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 19a0b37d06a2a5..f93f920b6aeca3 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -432,11 +432,11 @@ def TMM4: X86Reg<"tmm4", 4>;
def TMM5: X86Reg<"tmm5", 5>;
def TMM6: X86Reg<"tmm6", 6>;
def TMM7: X86Reg<"tmm7", 7>;
-}
// TMM register pairs
def TPAIRS : RegisterTuples<[sub_t0, sub_t1],
[(add TMM0, TMM2, TMM4, TMM6),
(add TMM1, TMM3, TMM5, TMM7)]>;
+}
// Floating point stack registers. These don't map one-to-one to the FP
// pseudo registers, but we still mark them as aliasing FP registers. That
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/88/builds/4173 Here is the relevant piece of the build log for the reference |
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It doesn't look like this made any difference. |
Ok, then I don't have any clue from source code. Let me reproduce it locally. |
smallp-o-p
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Nov 3, 2024
Should solve compile time regression.
NoumanAmir657
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Nov 4, 2024
Should solve compile time regression.
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Should solve compile time regression.