[CodeGen][Mips] Explicit ELF output file format for MIPS tests #114678

hpoussin · 2024-11-02T16:19:03Z

This will be required once MIPS architecture defaults to COFF files on Windows platforms.

llvmbot · 2024-11-02T16:19:36Z

@llvm/pr-subscribers-debuginfo

Author: Hervé Poussineau (hpoussin)

Changes

This will be required once MIPS architecture defaults to COFF files on Windows platforms.

Patch is 95.73 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/114678.diff

101 Files Affected:

(modified) llvm/test/CodeGen/Mips/Fast-ISel/br1.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/addressing-mode.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/atomic-min-max-64.ll (+4-4)
(modified) llvm/test/CodeGen/Mips/atomic-min-max.ll (+13-13)
(modified) llvm/test/CodeGen/Mips/brconeq.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/brconeqk.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/brconeqz.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/brconge.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/brcongt.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/brconle.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/brconlt.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/brconne.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/brconnek.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/brconnez.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/cconv/memory-layout.ll (+8-8)
(modified) llvm/test/CodeGen/Mips/cfi_offset.ll (+6-6)
(modified) llvm/test/CodeGen/Mips/dins.ll (+4-4)
(modified) llvm/test/CodeGen/Mips/dsp-r1.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/eh-return32.ll (+3-3)
(modified) llvm/test/CodeGen/Mips/eh-return64.ll (+4-4)
(modified) llvm/test/CodeGen/Mips/emit-big-cst.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/ex2.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/fpbr.ll (+6-6)
(modified) llvm/test/CodeGen/Mips/frame-address.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/jumptable_labels.ll (+3-3)
(modified) llvm/test/CodeGen/Mips/llvm-ir/add.ll (+15-15)
(modified) llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll (+11-11)
(modified) llvm/test/CodeGen/Mips/llvm-ir/select-int.ll (+15-15)
(modified) llvm/test/CodeGen/Mips/load-store-left-right.ll (+14-14)
(modified) llvm/test/CodeGen/Mips/mcount.ll (+6-6)
(modified) llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/mips64directive.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/2r.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll (+4-4)
(modified) llvm/test/CodeGen/Mips/msa/2rf.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/2rf_exup.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/2rf_float_int.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/2rf_fq.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/2rf_int_float.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/2rf_tq.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r-a.ll (+3-3)
(modified) llvm/test/CodeGen/Mips/msa/3r-b.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r-c.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r-d.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r-i.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r-m.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r-p.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r-s.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r-v.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r_4r.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3r_splat.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3rf.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3rf_4rf.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3rf_exdo.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3rf_float_int.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3rf_int_float.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/3rf_q.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/arithmetic_float.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/bit.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/bitcast.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/compare.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/compare_float.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/elm_copy.ll (+4-4)
(modified) llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/elm_insv.ll (+4-4)
(modified) llvm/test/CodeGen/Mips/msa/elm_move.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/endian.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/frameindex.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/i10.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/i5-a.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/i5-c.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/i5-m.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/i5_ld_st.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/i8.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/remat-ldi.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll (+4-4)
(modified) llvm/test/CodeGen/Mips/msa/special.ll (+4-4)
(modified) llvm/test/CodeGen/Mips/msa/spill.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/vec.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/msa/vecs10.ll (+2-2)
(modified) llvm/test/CodeGen/Mips/octeon.ll (+3-3)
(modified) llvm/test/CodeGen/Mips/prevent-hoisting.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selTBteqzCmpi.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selTBtnezCmpi.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selTBtnezSlti.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/seleq.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/seleqk.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selgek.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selgt.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selle.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selltk.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selne.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selnek.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/selpat.ll (+1-1)
(modified) llvm/test/CodeGen/Mips/unalignedload.ll (+6-6)
(modified) llvm/test/DebugInfo/Mips/tls.ll (+2-2)

diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
index 2f0f1a04a55886..b5bdf840facf46 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @b = global i32 1, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
index 37e49c2e8a428b..3462f1d2b9d463 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
 ; RUN:     < %s -verify-machineinstrs | FileCheck %s
 
 
diff --git a/llvm/test/CodeGen/Mips/addressing-mode.ll b/llvm/test/CodeGen/Mips/addressing-mode.ll
index bd8daf45be2c40..9d4363765c96af 100644
--- a/llvm/test/CodeGen/Mips/addressing-mode.ll
+++ b/llvm/test/CodeGen/Mips/addressing-mode.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s
 
 @g0 = common global i32 0, align 4
 @g1 = common global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll
index 5273f499cedec7..f3308c4b6ad12e 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
+; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
+; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
 
 define i64 @test_max(ptr nocapture %ptr, i64 signext %val) {
 ; MIPS-LABEL: test_max:
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll
index 3d3225509d1ae1..85bf6d02c7d8f2 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll
@@ -1,17 +1,17 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
-; RUN: llc -march=mips -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM
-; RUN: llc -march=mips -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6
-; RUN: llc -march=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL
-; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6
-; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL
-; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6
+; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
+; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6
+; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL
+; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6
+; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL
+; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6
+; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL
+; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6
 
 define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) {
 ; MIPS-LABEL: test_max_32:
diff --git a/llvm/test/CodeGen/Mips/brconeq.ll b/llvm/test/CodeGen/Mips/brconeq.ll
index ba7dc0f8540e6c..7c23db8d96fc49 100644
--- a/llvm/test/CodeGen/Mips/brconeq.ll
+++ b/llvm/test/CodeGen/Mips/brconeq.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @i = global i32 5, align 4
 @j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brconeqk.ll b/llvm/test/CodeGen/Mips/brconeqk.ll
index 4ee2f772ff68e0..98d8b07bc80910 100644
--- a/llvm/test/CodeGen/Mips/brconeqk.ll
+++ b/llvm/test/CodeGen/Mips/brconeqk.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @i = global i32 5, align 4
 @result = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/brconeqz.ll b/llvm/test/CodeGen/Mips/brconeqz.ll
index b8e7d1d12f9789..fbc50a7701b353 100644
--- a/llvm/test/CodeGen/Mips/brconeqz.ll
+++ b/llvm/test/CodeGen/Mips/brconeqz.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @i = global i32 5, align 4
 @result = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/brconge.ll b/llvm/test/CodeGen/Mips/brconge.ll
index 38e3a7c3706f54..4e91f4624aa6df 100644
--- a/llvm/test/CodeGen/Mips/brconge.ll
+++ b/llvm/test/CodeGen/Mips/brconge.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16
 
 @i = global i32 5, align 4
 @j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brcongt.ll b/llvm/test/CodeGen/Mips/brcongt.ll
index 3231811588fc14..1152167f3a8ab2 100644
--- a/llvm/test/CodeGen/Mips/brcongt.ll
+++ b/llvm/test/CodeGen/Mips/brcongt.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @i = global i32 5, align 4
 @j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brconle.ll b/llvm/test/CodeGen/Mips/brconle.ll
index e0ade5df237753..d68362f253a3a3 100644
--- a/llvm/test/CodeGen/Mips/brconle.ll
+++ b/llvm/test/CodeGen/Mips/brconle.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16
 
 @i = global i32 -5, align 4
 @j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brconlt.ll b/llvm/test/CodeGen/Mips/brconlt.ll
index f3dbb9607eaffb..522db0d9e2da5c 100644
--- a/llvm/test/CodeGen/Mips/brconlt.ll
+++ b/llvm/test/CodeGen/Mips/brconlt.ll
@@ -1,5 +1,5 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc  -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mips-elf -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
 
 @i = global i32 5, align 4
 @j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brconne.ll b/llvm/test/CodeGen/Mips/brconne.ll
index 5c3a0ef3432914..e673727def7d9f 100644
--- a/llvm/test/CodeGen/Mips/brconne.ll
+++ b/llvm/test/CodeGen/Mips/brconne.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @i = global i32 5, align 4
 @j = global i32 5, align 4
diff --git a/llvm/test/CodeGen/Mips/brconnek.ll b/llvm/test/CodeGen/Mips/brconnek.ll
index 30c32825da52e4..f963be59c12f41 100644
--- a/llvm/test/CodeGen/Mips/brconnek.ll
+++ b/llvm/test/CodeGen/Mips/brconnek.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @j = global i32 5, align 4
 @result = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/brconnez.ll b/llvm/test/CodeGen/Mips/brconnez.ll
index 5f8b54e9cbb50d..15ba7c16cb3dde 100644
--- a/llvm/test/CodeGen/Mips/brconnez.ll
+++ b/llvm/test/CodeGen/Mips/brconnez.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @j = global i32 0, align 4
 @result = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
index dae4bfc2260901..c95fe09de20e70 100644
--- a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
+++ b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
@@ -1,14 +1,14 @@
-; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mips-elf < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mipsel-elf < %s | FileCheck --check-prefixes=ALL,O32 %s
 
-; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64el-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
 
-; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64el-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
 
-; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64-elf -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64el-elf -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
 
 ; Test the memory layout for all ABI's and byte orders as specified by section
 ; 4 of MD00305 (MIPS ABIs Described).
diff --git a/llvm/test/CodeGen/Mips/cfi_offset.ll b/llvm/test/CodeGen/Mips/cfi_offset.ll
index 217adda59468a9..e55924e2f5353e 100644
--- a/llvm/test/CodeGen/Mips/cfi_offset.ll
+++ b/llvm/test/CodeGen/Mips/cfi_offset.ll
@@ -1,9 +1,9 @@
-; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
-; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
-; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
-; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
-; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
-; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
+; RUN: llc -mtriple=mips-elf -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
+; RUN: llc -mtriple=mipsel-elf -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
+; RUN: llc -mtriple=mips-elf -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
+; RUN: llc -mtriple=mipsel-elf -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
+; RUN: llc -mtriple=mips-elf -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
+; RUN: llc -mtriple=mipsel-elf -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
 
 @var = global double 0.0
 
diff --git a/llvm/test/CodeGen/Mips/dins.ll b/llvm/test/CodeGen/Mips/dins.ll
index 4deb7455a80128..cdb8f419eb2be1 100644
--- a/llvm/test/CodeGen/Mips/dins.ll
+++ b/llvm/test/CodeGen/Mips/dins.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \
+; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \
 ; RUN:   -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2
-; RUN: llc -O2 -verify-machineinstrs -march=mips -mcpu=mips32r2 < %s -o - \
+; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mcpu=mips32r2 < %s -o - \
 ; RUN:   | FileCheck %s -check-prefix=MIPS32R2
-; RUN: llc -O2 -verify-machineinstrs -march=mips -mattr=mips16 < %s -o - \
+; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mattr=mips16 < %s -o - \
 ; RUN:   | FileCheck %s -check-prefix=MIPS16
-; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \
+; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \
 ; RUN:   -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32
 
 ; #include <stdint.h>
diff --git a/llvm/test/CodeGen/Mips/dsp-r1.ll b/llvm/test/CodeGen/Mips/dsp-r1.ll
index 0ec23b9d7fd770..7a661d6c70514e 100644
--- a/llvm/test/CodeGen/Mips/dsp-r1.ll
+++ b/llvm/test/CodeGen/Mips/dsp-r1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \
+; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \
 ; RUN:     FileCheck %s
 
 define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
diff --git a/llvm/test/CodeGen/Mips/eh-return32.ll b/llvm/test/CodeGen/Mips/eh-return32.ll
index 983fc6f7788c78..0c60c473109523 100644
--- a/llvm/test/CodeGen/Mips/eh-return32.ll
+++ b/llvm/test/CodeGen/Mips/eh-return32.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -mcpu=mips32   -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6
+; RUN: llc -mtriple=mipsel-elf -mcpu=mips32   -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6
 
 declare void @llvm.eh.return.i32(i32, ptr)
 declare void @foo(...)
diff --git a/llvm/test/CodeGen/Mips/eh-return64.ll b/llvm/test/CodeGen/Mips/eh-return64.ll
index 9ae2f00d46c1e9..f5a547a3b608c0 100644
--- a/llvm/test/CodeGen/Mips/eh-return64.ll
+++ b/llvm/test/CodeGen/Mips/eh-return64.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips64el -mcpu=mips4    -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mips64el -mcpu=mips64   -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6
+; RUN: llc -mtriple=mips64el-elf -mcpu=mips4    -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mips64el-elf -mcpu=mips64   -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6
 
 declare void @llvm.eh.return.i64(i64, ptr)
 declare void @foo(...)
diff --git a/llvm/test/CodeGen/Mips/emit-big-cst.ll b/llvm/test/CodeGen/Mips/emit-big-cst.ll
index cd0666cfd3fc24..5171e22abab6f4 100644
--- a/llvm/test/CodeGen/Mips/emit-big-cst.ll
+++ b/llvm/test/CodeGen/Mips/emit-big-cst.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=BE
-; RUN: llc -march=mipsel < %s | FileCheck %s --check-prefix=LE
+; RUN: llc -mtriple=mips-elf < %s | FileCheck %s --check-prefix=BE
+; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s --check-prefix=LE
 ; Check assembly printing of odd constants.
 
 ; BE-LABEL: bigCst:
diff --git a/llvm/test/CodeGen/Mips/ex2.ll b/llvm/test/CodeGen/Mips/ex2.ll
index 79aabfcbbfc437..d0fa4058e41e7f 100644
--- a/llvm/test/CodeGen/Mips/ex2.ll
+++ b/llvm/test/CodeGen/Mips/ex2.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
 
 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
 @_ZTIPKc = external constant ptr
diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll
index 251c5392575b2d..7193a426ab0d21 100644
--- a/llvm/test/CodeGen/Mips/...
[truncated]

hpoussin · 2024-11-11T21:07:18Z

Ping.
I don't think the timeout failure of test "tools/lldb-dap/evaluate/TestDAP_evaluate.py" on Linux buildbot is due to my commit.

brad0 · 2024-11-17T07:39:16Z

cc @yingopq

hpoussin · 2024-12-09T06:27:44Z

Ping.

hpoussin · 2024-12-17T19:18:16Z

Ping @brad0, @yingopq, @FlyGoat, @wzssyqa, @mstorsjo

yingopq · 2024-12-18T03:04:44Z

LGTM.

wzssyqa · 2024-12-20T09:35:11Z

I don't think that we should have these test case modification.
I mean that ELF should be kept as the default value for MIPS.

wzssyqa · 2024-12-20T09:38:18Z

LLVM doesn't expect that the behavior of same command has different behaviors on different platforms.

Aka, you should always use something like --triple=mips-coff if you need the object to be a COFF.

brad0 · 2024-12-20T09:38:19Z

@MaskRay

mstorsjo · 2024-12-20T14:56:47Z

I don't think that we should have these test case modification. I mean that ELF should be kept as the default value for MIPS.

Indeed, even if we make COFF the default for the OS windows on MIPS, it shouldn't change anything about when we run with an OS-less triple like llc -mtriple=mipsel, so I don't see why this is needed.

wzssyqa · 2024-12-22T02:30:59Z

On My AARCH64 Mac

syq@syqs-iMac> clang --target=aarch64 -c xx.c 
syq@syqs-iMac> file xx.o 
xx.o: ELF 64-bit LSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
syq@syqs-iMac> clang --target=aarch64-apple-darwin -c xx.c
syq@syqs-iMac> file xx.o
xx.o: Mach-O 64-bit object arm64

yingopq · 2024-12-23T01:52:12Z

LLVM doesn't expect that the behavior of same command has different behaviors on different platforms.

Aka, you should always use something like --triple=mips-coff if you need the object to be a COFF.

Thanks, I got it.

MaskRay · 2024-12-23T01:55:58Z

The thumb of rule is: -mtriple=mipsel defaults to ELF, even if we don't write '-elf' or '-linux'. Yes, ELF is the favored object file format, which gets this shortcut, while other object file formats need a lengthy target triple.

[CodeGen][Mips] Explicit ELF output file format for MIPS tests

4a6f456

This will be required once MIPS architecture defaults to COFF files on Windows platforms.

llvmbot added the debuginfo label Nov 2, 2024

hpoussin mentioned this pull request Nov 2, 2024

[MC][Mips] Add MipsWinCOFFObjectWriter/MipsWinCOFFStreamer #114611

Merged

Merge branch 'main' into clang-mips-coff-7

d3a8112

wzssyqa closed this Dec 22, 2024

hpoussin mentioned this pull request Jan 21, 2025

[clang][MIPS] Add support for mipsel-windows-* targets #107744

Closed

hpoussin deleted the clang-mips-coff-7 branch January 21, 2025 17:50

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[CodeGen][Mips] Explicit ELF output file format for MIPS tests #114678

[CodeGen][Mips] Explicit ELF output file format for MIPS tests #114678

Uh oh!

hpoussin commented Nov 2, 2024

Uh oh!

llvmbot commented Nov 2, 2024

Uh oh!

hpoussin commented Nov 11, 2024

Uh oh!

brad0 commented Nov 17, 2024

Uh oh!

hpoussin commented Dec 9, 2024

Uh oh!

hpoussin commented Dec 17, 2024

Uh oh!

yingopq commented Dec 18, 2024

Uh oh!

wzssyqa commented Dec 20, 2024

Uh oh!

wzssyqa commented Dec 20, 2024

Uh oh!

brad0 commented Dec 20, 2024

Uh oh!

mstorsjo commented Dec 20, 2024

Uh oh!

wzssyqa commented Dec 22, 2024 •

edited

Loading

Uh oh!

yingopq commented Dec 23, 2024

Uh oh!

MaskRay commented Dec 23, 2024

Uh oh!

Uh oh!

[CodeGen][Mips] Explicit ELF output file format for MIPS tests #114678

[CodeGen][Mips] Explicit ELF output file format for MIPS tests #114678

Uh oh!

Conversation

hpoussin commented Nov 2, 2024

Uh oh!

llvmbot commented Nov 2, 2024

Uh oh!

hpoussin commented Nov 11, 2024

Uh oh!

brad0 commented Nov 17, 2024

Uh oh!

hpoussin commented Dec 9, 2024

Uh oh!

hpoussin commented Dec 17, 2024

Uh oh!

yingopq commented Dec 18, 2024

Uh oh!

wzssyqa commented Dec 20, 2024

Uh oh!

wzssyqa commented Dec 20, 2024

Uh oh!

brad0 commented Dec 20, 2024

Uh oh!

mstorsjo commented Dec 20, 2024

Uh oh!

wzssyqa commented Dec 22, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

yingopq commented Dec 23, 2024

Uh oh!

MaskRay commented Dec 23, 2024

Uh oh!

Uh oh!

wzssyqa commented Dec 22, 2024 •

edited

Loading