[MLIR][Affine] Fix a crash with invalid cachesize

[SwapnilGhanshyala]

Updated LoopTiling::runOnOperation() to signal pass failure incase the set cachesize is equal to zero.

Fixes #64979.

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@llvm/pr-subscribers-mlir-affine

Author: None (SwapnilGhanshyala)

Changes

Updated LoopTiling::runOnOperation() to signal pass failure incase the set cachesize is invalid, i.e., less than or equal to zero.

#64979 is the reporting issue.

---

Full diff: https://github.com/llvm/llvm-project/pull/114722.diff

1 Files Affected:

• (modified) mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp (+6)

diff --git a/mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp b/mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp
index c8400dfe8cd5c7..b4cf9e13729a30 100644
--- a/mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp
+++ b/mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp
@@ -173,6 +173,12 @@ void LoopTiling::getTileSizes(ArrayRef<AffineForOp> band,
 }
 
 void LoopTiling::runOnOperation() {
+  if (cacheSizeInKiB <= 0) {
+    getOperation().emitError(
+        "illegal argument: '--affine-loop-tile=cache-size' cannot be "
+        "less than or equal to zero. \nAborted!");
+    return signalPassFailure();
+  }
   // Bands of loops to tile.
   std::vector<SmallVector<AffineForOp, 6>> bands;
   getTileableBands(getOperation(), &bands);

[bondhugula]

Cache size zero can be considered a valid input and should not signal pass failure for it. Fixed here: #130526