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Nov 9, 2024
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AMDGPU: Default to selecting frame indexes to SGPRs #115060

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5 changes: 4 additions & 1 deletion llvm/lib/Target/AMDGPU/SIInstructions.td
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Expand Up @@ -2175,8 +2175,11 @@ foreach vt = [i32, p3, p5, p6, p2] in {
>;
}

// FIXME: The register bank of the frame index should depend on the
// users, and transitive users of the add. We may require an
// unnecessary copy from SGPR to VGPR.
def : GCNPat <
(p5 frameindex:$fi),
(VGPRImm<(p5 frameindex)>:$fi),
(V_MOV_B32_e32 (p5 (frameindex_to_targetframeindex $fi)))
>;

Expand Down
5 changes: 3 additions & 2 deletions llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
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Expand Up @@ -364,9 +364,10 @@ entry:

; FUNC-LABEL: ptrtoint:
; SI-NOT: ds_write
; SI: s_add_i32 [[S_ADD_OFFSET:s[0-9]+]], s{{[0-9]+}}, 5
; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; SI: v_add_{{[iu]}}32_e32 [[ADD_OFFSET:v[0-9]+]], vcc, 5,
; SI: buffer_load_dword v{{[0-9]+}}, [[ADD_OFFSET:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offen ;
; SI: v_mov_b32_e32 [[V_ADD_OFFSET:v[0-9]+]], [[S_ADD_OFFSET]]
; SI: buffer_load_dword v{{[0-9]+}}, [[V_ADD_OFFSET:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offen ;
define amdgpu_kernel void @ptrtoint(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
%alloca = alloca [16 x i32], addrspace(5)
%tmp0 = getelementptr [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a
Expand Down
72 changes: 31 additions & 41 deletions llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
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Expand Up @@ -147,19 +147,14 @@ define amdgpu_kernel void @stored_fi_to_global_2_small_objects(ptr addrspace(1)

; GCN-LABEL: {{^}}kernel_stored_fi_to_global_huge_frame_offset:
; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}

; FIXME: Re-initialize
; GCN: v_mov_b32_e32 [[BASE_0_1:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4{{$}}

; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
; GCN-DAG: v_add_i32_e32 [[BASE_1_OFF_1:v[0-9]+]], vcc, 0x3ffc, [[BASE_0_1]]

; GCN-DAG: v_mov_b32_e32 [[V_BASE_1_OFF:v[0-9]+]], 0x4000{{$}}
; GCN: buffer_store_dword [[K]], [[V_BASE_1_OFF]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}

; GCN: v_add_i32_e32 [[BASE_1_OFF_2:v[0-9]+]], vcc, 56, [[BASE_0_1]]
; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}

; GCN: buffer_store_dword [[BASE_1_OFF_2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
; GCN: buffer_store_dword [[V_BASE_1_OFF]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_kernel void @kernel_stored_fi_to_global_huge_frame_offset(ptr addrspace(1) %ptr) #0 {
%tmp0 = alloca [4096 x i32], addrspace(5)
%tmp1 = alloca [4096 x i32], addrspace(5)
Expand All @@ -171,20 +166,20 @@ define amdgpu_kernel void @kernel_stored_fi_to_global_huge_frame_offset(ptr addr
ret void
}

; FIXME: Shift of SP repeated twice
; GCN-LABEL: {{^}}func_stored_fi_to_global_huge_frame_offset:
; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
; GCN-DAG: v_lshr_b32_e64 [[FI_TMP_0:v[0-9]+]], s32, 6
; GCN-DAG: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:4{{$}}

; GCN: v_lshr_b32_e64 [[FI_TMP:v[0-9]+]], s32, 6
; GCN: v_add_i32_e32 [[BASE_0_1:v[0-9]+]], vcc, 4, [[FI_TMP]]{{$}}

; GCN-DAG: v_add_i32_e32 [[FI_0:v[0-9]+]], vcc, 0x4000, [[FI_TMP_0]]{{$}}
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
; GCN-DAG: v_add_i32_e32 [[BASE_1_OFF_1:v[0-9]+]], vcc, 0x3ffc, [[BASE_0_1]]

; GCN: v_add_i32_e32 [[BASE_1_OFF_2:v[0-9]+]], vcc, 56, [[BASE_0_1]]
; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}

; GCN: buffer_store_dword [[BASE_1_OFF_2]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
; GCN: buffer_store_dword [[K]], [[FI_0]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
; GCN: v_lshr_b32_e64 [[FI_TMP_1:v[0-9]+]], s32, 6
; GCN: v_add_i32_e32 [[BASE_0_1:v[0-9]+]], vcc, 60, [[FI_TMP_1]]{{$}}
; GCN: buffer_store_dword [[BASE_0_1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
define void @func_stored_fi_to_global_huge_frame_offset(ptr addrspace(1) %ptr) #0 {
%tmp0 = alloca [4096 x i32], addrspace(5)
%tmp1 = alloca [4096 x i32], addrspace(5)
Expand Down Expand Up @@ -217,9 +212,9 @@ entry:
ret void
}

; FIXME: This is broken, and the sgpr input just gets replaced with a VGPR
; GCN-LABEL: {{^}}func_alloca_offset0__use_asm_sgpr:
; GCN: v_lshr_b32_e64 [[FI:v[0-9]+]], s32, 6
; GCN: s_lshr_b32 [[FI:s[0-9]+]], s32, 6
; GCN-NOT: [[FI]]
; GCN: ; use [[FI]]
define void @func_alloca_offset0__use_asm_sgpr() {
%alloca = alloca i32, addrspace(5)
Expand All @@ -238,9 +233,9 @@ define void @func_alloca_offset0__use_asm_vgpr() {
}

; GCN-LABEL: {{^}}func_alloca_offset0__use_asm_phys_sgpr:
; GCN: s_lshr_b32 s8, s32, 6
; GCN: s_lshr_b32 [[FI:s[0-9]+]], s32, 6
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use s8
; GCN-NEXT: ; use [[FI]]
define void @func_alloca_offset0__use_asm_phys_sgpr() {
%alloca = alloca i32, addrspace(5)
call void asm sideeffect "; use $0", "{s8}"(ptr addrspace(5) %alloca)
Expand All @@ -258,12 +253,11 @@ define void @func_alloca_offset0__use_asm_phys_vgpr() {
}

; GCN-LABEL: {{^}}func_alloca_offset_use_asm_sgpr:
; GCN: v_lshr_b32_e64 [[FI0_TMP0:v[0-9]+]], s32, 6
; GCN-NEXT: v_add_i32_e32 [[FI0:v[0-9]+]], vcc, 16, [[FI0_TMP0]]
; GCN: s_lshr_b32 [[FI0_TMP0:s[0-9]+]], s32, 6
; GCN-NEXT: s_add_i32 [[FI0:s[0-9]+]], [[FI0_TMP0]], 16

; GCN: v_lshr_b32_e64 [[TMP:v[0-9]+]], s32, 6
; GCN-NEXT: s_movk_i32 vcc_lo, 0x4010
; GCN-NEXT: v_add_i32_e32 [[TMP]], vcc, vcc_lo, [[TMP]]
; GCN: s_lshr_b32 [[TMP:s[0-9]+]], s32, 6
; GCN-NEXT: s_addk_i32 [[TMP]], 0x4010
; GCN-NEXT: ;;#ASMSTART
; GCN: ; use [[TMP]]
define void @func_alloca_offset_use_asm_sgpr() {
Expand All @@ -274,19 +268,17 @@ define void @func_alloca_offset_use_asm_sgpr() {
ret void
}

; FIXME: Shouldn't need to materialize constant
; GCN-LABEL: {{^}}func_alloca_offset_use_asm_vgpr:
; GCN: v_lshr_b32_e64 [[FI0_TMP:v[0-9]+]], s32, 6
; GCN-NEXT: v_add_i32_e32 [[FI0:v[0-9]+]], vcc, 16, [[FI0_TMP]]
; GCN: s_lshr_b32 [[S_FI:s[0-9]+]], s32, 6
; GCN: v_lshr_b32_e64 [[V_FI:v[0-9]+]], s32, 6
; GCN: s_movk_i32 vcc_lo, 0x4010
; GCN: s_add_i32 [[S_FI]], [[S_FI]], 16
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use [[FI0]]
; GCN-NEXT: ; use [[S_FI]]
; GCN-NEXT: ;;#ASMEND

; GCN: v_lshr_b32_e64 [[FI1_TMP:v[0-9]+]], s32, 6
; GCN-NEXT: s_movk_i32 vcc_lo, 0x4010
; GCN-NEXT: v_add_i32_e32 [[FI1:v[0-9]+]], vcc, vcc_lo, [[FI1_TMP]]
; GCN-NEXT: v_add_i32_e32 [[V_FI:v[0-9]+]], vcc, vcc_lo, [[V_FI]]
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use [[FI1]]
; GCN-NEXT: ; use [[V_FI]]
; GCN-NEXT: ;;#ASMEND
define void @func_alloca_offset_use_asm_vgpr() {
%alloca0 = alloca [4096 x i32], align 16, addrspace(5)
Expand All @@ -296,17 +288,15 @@ define void @func_alloca_offset_use_asm_vgpr() {
ret void
}

; FIXME: Using VGPR for SGPR input
; GCN-LABEL: {{^}}kernel_alloca_offset_use_asm_sgpr:
; GCN: v_mov_b32_e32 v0, 16
; GCN: s_mov_b32 [[FI0:s[0-9]+]], 16
; GCN-NOT: v0
; GCN: ;;#ASMSTART
; GCN-NEXT: ; use v0
; GCN-NEXT: ; use [[FI0]]
; GCN-NEXT: ;;#ASMEND

; GCN: v_mov_b32_e32 v0, 0x4010
; GCN: s_movk_i32 [[FI1:s[0-9]+]], 0x4010
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; use v0
; GCN-NEXT: ; use [[FI1]]
; GCN-NEXT: ;;#ASMEND
define amdgpu_kernel void @kernel_alloca_offset_use_asm_sgpr() {
%alloca0 = alloca [4096 x i32], align 16, addrspace(5)
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/commute-compares.ll
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Expand Up @@ -699,8 +699,8 @@ define amdgpu_kernel void @commute_uno_2.0_f64(ptr addrspace(1) %out, ptr addrsp
; GCN-LABEL: {{^}}commute_frameindex:
; XGCN: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}}

; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
; GCN: v_cmp_eq_u32_e32 vcc, v{{[0-9]+}}, [[FI]]
; GCN: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
; GCN: v_cmp_eq_u32_e32 vcc, [[FI]], v{{[0-9]+}}
define amdgpu_kernel void @commute_frameindex(ptr addrspace(1) nocapture %out) #0 {
entry:
%stack0 = alloca i32, addrspace(5)
Expand Down
122 changes: 55 additions & 67 deletions llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
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Expand Up @@ -15,18 +15,16 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX940-SDAG-LABEL: soff1_voff1:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, v1, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, s0, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
Expand Down Expand Up @@ -145,18 +143,17 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX940-SDAG-LABEL: soff1_voff2:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v1
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v2
; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
Expand Down Expand Up @@ -282,18 +279,17 @@ define amdgpu_kernel void @soff1_voff4(i32 %soff) {
; GFX940-SDAG-LABEL: soff1_voff4:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v2
; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
Expand Down Expand Up @@ -419,19 +415,17 @@ define amdgpu_kernel void @soff2_voff1(i32 %soff) {
; GFX940-SDAG-LABEL: soff2_voff1:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 1
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, v1, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, s0, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
Expand Down Expand Up @@ -556,14 +550,13 @@ define amdgpu_kernel void @soff2_voff2(i32 %soff) {
; GFX940-SDAG-LABEL: soff2_voff2:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 1
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v1
; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v2
; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
Expand Down Expand Up @@ -698,14 +691,13 @@ define amdgpu_kernel void @soff2_voff4(i32 %soff) {
; GFX940-SDAG-LABEL: soff2_voff4:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 1
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v2
; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
Expand Down Expand Up @@ -840,19 +832,17 @@ define amdgpu_kernel void @soff4_voff1(i32 %soff) {
; GFX940-SDAG-LABEL: soff4_voff1:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 2
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, v1, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 1, v0
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, s0, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
; GFX940-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
; GFX940-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX940-SDAG-NEXT: scratch_store_byte v1, v2, off sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
; GFX940-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
Expand Down Expand Up @@ -977,14 +967,13 @@ define amdgpu_kernel void @soff4_voff2(i32 %soff) {
; GFX940-SDAG-LABEL: soff4_voff2:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 2
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v1
; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 1, v2
; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, 2, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
Expand Down Expand Up @@ -1119,17 +1108,16 @@ define amdgpu_kernel void @soff4_voff4(i32 %soff) {
; GFX940-SDAG-LABEL: soff4_voff4:
; GFX940-SDAG: ; %bb.0: ; %bb
; GFX940-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX940-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX940-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-SDAG-NEXT: s_lshl_b32 s0, s0, 2
; GFX940-SDAG-NEXT: v_add_u32_e32 v1, s0, v1
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 2
; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: v_mov_b32_e32 v3, s0
; GFX940-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, v3
; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: scratch_store_byte v0, v1, off offset:2 sc0 sc1
; GFX940-SDAG-NEXT: scratch_store_byte v0, v2, off offset:2 sc0 sc1
; GFX940-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX940-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX940-SDAG-NEXT: v_mov_b32_e32 v1, 4
Expand Down
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