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[GISel][RISCV][AMDGPU] Add G_SHL, G_LSHR, G_ASHR to binop_left_to_zero. #115089

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Merged
merged 3 commits into from
Nov 7, 2024
Merged

[GISel][RISCV][AMDGPU] Add G_SHL, G_LSHR, G_ASHR to binop_left_to_zero. #115089

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db052d2
[GISel][RISCV][AMDGPU] Add G_SHL, G_LSHR, G_ASHR to binop_left_to_zero.
topperc Nov 5, 2024
49d0e0d
Merge remote-tracking branch 'origin/main' into pr/shift-of-zero
topperc Nov 6, 2024
39301a4
Merge remote-tracking branch 'origin/main' into pr/shift-of-zero
topperc Nov 6, 2024
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3 changes: 2 additions & 1 deletion llvm/include/llvm/Target/GlobalISel/Combine.td
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Original file line number Diff line number Diff line change
Expand Up @@ -566,7 +566,8 @@ def binop_same_val: GICombineRule<
// Fold (0 op x) - > 0
def binop_left_to_zero: GICombineRule<
(defs root:$root),
(match (wip_match_opcode G_SDIV, G_UDIV, G_SREM, G_UREM):$root,
(match (wip_match_opcode G_SHL, G_LSHR, G_ASHR, G_SDIV, G_UDIV, G_SREM,
G_UREM):$root,
[{ return Helper.matchOperandIsZero(*${root}, 1); }]),
(apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
>;
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
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Expand Up @@ -348,14 +348,14 @@ body: |
; GFX6-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %shl:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: $vgpr0 = COPY %shl(s32)
; GFX6-NEXT: %extend:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: $vgpr0 = COPY %extend(s32)
;
; GFX9-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %shl:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: $vgpr0 = COPY %shl(s32)
; GFX9-NEXT: %extend:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: $vgpr0 = COPY %extend(s32)
%zero:_(s16) = G_CONSTANT i16 0
%extend:_(s32) = G_ZEXT %zero:_(s16)
%shiftamt:_(s16) = G_CONSTANT i16 16
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76 changes: 32 additions & 44 deletions llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
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Expand Up @@ -270,14 +270,12 @@ define i128 @fptosi_f64_to_i128(double %x) {
; GISEL-NEXT: s_andn2_saveexec_b64 s[8:9], s[16:17]
; GISEL-NEXT: s_cbranch_execz .LBB0_6
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
; GISEL-NEXT: v_sub_co_u32_e32 v6, vcc, 0x433, v6
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v6
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v6, v[4:5]
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, 0
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x433, v6
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v10, 0
; GISEL-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
Expand Down Expand Up @@ -640,14 +638,12 @@ define i128 @fptoui_f64_to_i128(double %x) {
; GISEL-NEXT: s_andn2_saveexec_b64 s[8:9], s[16:17]
; GISEL-NEXT: s_cbranch_execz .LBB1_6
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
; GISEL-NEXT: v_sub_co_u32_e32 v6, vcc, 0x433, v6
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v6
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v6, v[4:5]
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, 0
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x433, v6
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v10, 0
; GISEL-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
Expand Down Expand Up @@ -1003,13 +999,11 @@ define i128 @fptosi_f32_to_i128(float %x) {
; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17]
; GISEL-NEXT: s_cbranch_execz .LBB2_6
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x96, v6
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[4:5]
; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x96, v6
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v4, v9, 0
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v4, v10, 0
Expand Down Expand Up @@ -1360,13 +1354,11 @@ define i128 @fptoui_f32_to_i128(float %x) {
; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17]
; GISEL-NEXT: s_cbranch_execz .LBB3_6
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x96, v6
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[4:5]
; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x96, v6
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[4:5]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v4, v9, 0
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v4, v10, 0
Expand Down Expand Up @@ -1740,13 +1732,11 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17]
; GISEL-NEXT: s_cbranch_execz .LBB6_6
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x86, v5
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[7:8]
; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x86, v5
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[7:8]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GISEL-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v9
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1
Expand Down Expand Up @@ -2091,13 +2081,11 @@ define i128 @fptoui_bf16_to_i128(bfloat %x) {
; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17]
; GISEL-NEXT: s_cbranch_execz .LBB7_6
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x86, v5
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[7:8]
; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x86, v5
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[7:8]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GISEL-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v9
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1
Expand Down
4 changes: 0 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
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Expand Up @@ -156,18 +156,14 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: andi a1, a2, 255
; RV32I-NEXT: slli a2, a1, 8
; RV32I-NEXT: slli a3, zero, 8
; RV32I-NEXT: srli a1, a1, 24
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret
;
; RV32ZBKB-LABEL: packh_i64_2:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: andi a1, a2, 255
; RV32ZBKB-NEXT: slli a3, zero, 8
; RV32ZBKB-NEXT: srli a1, a1, 24
; RV32ZBKB-NEXT: or a1, a3, a1
; RV32ZBKB-NEXT: packh a0, a0, a2
; RV32ZBKB-NEXT: ret
%and = and i64 %a, 255
Expand Down
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