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[RISCV][GISel] Implement zexti32/zexti16 ComplexPatterns. #115097

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Merged
merged 2 commits into from
Nov 6, 2024
Merged

[RISCV][GISel] Implement zexti32/zexti16 ComplexPatterns. #115097

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f8801c3
[RISCV][GISel] Implement zexti32/zexti16 ComplexPatterns.
topperc Nov 5, 2024
7b51888
fixup! Use m_SpecificICst.
topperc Nov 6, 2024
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24 changes: 24 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,12 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;

ComplexRendererFns selectZExtBits(MachineOperand &Root, unsigned Bits) const;
template <unsigned Bits>
ComplexRendererFns selectZExtBits(MachineOperand &Root) const {
return selectZExtBits(Root, Bits);
}

ComplexRendererFns selectSHXADDOp(MachineOperand &Root, unsigned ShAmt) const;
template <unsigned ShAmt>
ComplexRendererFns selectSHXADDOp(MachineOperand &Root) const {
Expand Down Expand Up @@ -242,6 +248,24 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}};
}

InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectZExtBits(MachineOperand &Root,
unsigned Bits) const {
if (!Root.isReg())
return std::nullopt;
Register RootReg = Root.getReg();

Register RegX;
uint64_t Mask = maskTrailingOnes<uint64_t>(Bits);
if (mi_match(RootReg, *MRI, m_GAnd(m_Reg(RegX), m_SpecificICst(Mask)))) {
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};
}

// TODO: Use computeKnownBits.

return std::nullopt;
}

InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root,
unsigned ShAmt) const {
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVGISel.td
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Expand Up @@ -96,6 +96,11 @@ def gi_sh2add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<2>">,
def gi_sh3add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<3>">,
GIComplexPatternEquiv<sh3add_uw_op>;

def gi_zexti32 : GIComplexOperandMatcher<s64, "selectZExtBits<32>">,
GIComplexPatternEquiv<zexti32>;
def gi_zexti16 : GIComplexOperandMatcher<s32, "selectZExtBits<16>">,
GIComplexPatternEquiv<zexti16>;

// Ptr type used in patterns with GlobalISelEmitter
def PtrVT : PtrValueTypeByHwMode<XLenVT, 0>;

Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
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Expand Up @@ -16,9 +16,7 @@ define i32 @pack_i32(i32 %a, i32 %b) nounwind {
;
; RV32ZBKB-LABEL: pack_i32:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: zext.h a0, a0
; RV32ZBKB-NEXT: slli a1, a1, 16
; RV32ZBKB-NEXT: or a0, a1, a0
; RV32ZBKB-NEXT: pack a0, a0, a1
; RV32ZBKB-NEXT: ret
%shl = and i32 %a, 65535
%shl1 = shl i32 %b, 16
Expand Down
15 changes: 3 additions & 12 deletions llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
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Expand Up @@ -85,10 +85,7 @@ define i64 @pack_i64(i64 %a, i64 %b) nounwind {
;
; RV64ZBKB-LABEL: pack_i64:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: slli a0, a0, 32
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: slli a1, a1, 32
; RV64ZBKB-NEXT: or a0, a1, a0
; RV64ZBKB-NEXT: pack a0, a0, a1
; RV64ZBKB-NEXT: ret
%shl = and i64 %a, 4294967295
%shl1 = shl i64 %b, 32
Expand All @@ -109,12 +106,9 @@ define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {
;
; RV64ZBKB-LABEL: pack_i64_2:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: slli a0, a0, 32
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: slli a1, a1, 32
; RV64ZBKB-NEXT: srli a1, a1, 32
; RV64ZBKB-NEXT: slli a1, a1, 32
; RV64ZBKB-NEXT: or a0, a1, a0
; RV64ZBKB-NEXT: pack a0, a0, a1
; RV64ZBKB-NEXT: ret
%zexta = zext i32 %a to i64
%zextb = zext i32 %b to i64
Expand Down Expand Up @@ -343,10 +337,7 @@ define i64 @pack_i64_allWUsers(i32 signext %0, i32 signext %1, i32 signext %2) {
; RV64ZBKB-NEXT: add a0, a1, a0
; RV64ZBKB-NEXT: slli a0, a0, 32
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: slli a0, a0, 32
; RV64ZBKB-NEXT: slli a2, a2, 32
; RV64ZBKB-NEXT: srli a2, a2, 32
; RV64ZBKB-NEXT: or a0, a0, a2
; RV64ZBKB-NEXT: pack a0, a2, a0
; RV64ZBKB-NEXT: ret
%4 = add i32 %1, %0
%5 = zext i32 %4 to i64
Expand Down
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