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[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. #115236

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Merged
merged 5 commits into from
Nov 7, 2024
Merged

[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. #115236

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f9ac147
[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64.
topperc Oct 18, 2024
69746ca
Merge remote-tracking branch 'origin/main' into pr/gisel-itofp
topperc Nov 7, 2024
5899f5e
fixup! Use computeNumSignBits.
topperc Nov 7, 2024
cbdf1a2
fixup! Add combines_for_extload to RISCVPostLegalizerCombiner.
topperc Nov 7, 2024
9379a50
Merge remote-tracking branch 'origin/main' into pr/gisel-itofp
topperc Nov 7, 2024
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27 changes: 27 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,12 @@ class RISCVInstructionSelector : public InstructionSelector {
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;

ComplexRendererFns selectSExtBits(MachineOperand &Root, unsigned Bits) const;
template <unsigned Bits>
ComplexRendererFns selectSExtBits(MachineOperand &Root) const {
return selectSExtBits(Root, Bits);
}

ComplexRendererFns selectZExtBits(MachineOperand &Root, unsigned Bits) const;
template <unsigned Bits>
ComplexRendererFns selectZExtBits(MachineOperand &Root) const {
Expand Down Expand Up @@ -248,6 +254,27 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}};
}

InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectSExtBits(MachineOperand &Root,
unsigned Bits) const {
if (!Root.isReg())
return std::nullopt;
Register RootReg = Root.getReg();
MachineInstr *RootDef = MRI->getVRegDef(RootReg);

if (RootDef->getOpcode() == TargetOpcode::G_SEXT_INREG &&
RootDef->getOperand(2).getImm() == Bits) {
return {
{[=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }}};
}

unsigned Size = MRI->getType(RootReg).getScalarSizeInBits();
if ((Size - KB->computeNumSignBits(RootReg)) < Bits)
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};

return std::nullopt;
}

InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectZExtBits(MachineOperand &Root,
unsigned Bits) const {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -542,9 +542,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.libcallFor(ST.is64Bit(), {{s128, s32}, {s128, s64}});

getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
.legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {s32, sXLen})))
.legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {sXLen})))
.widenScalarToNextPow2(1)
.minScalar(1, s32)
.minScalar(1, sXLen)
.libcallFor({{s32, s32}, {s64, s32}, {s32, s64}, {s64, s64}})
.libcallFor(ST.is64Bit(), {{s32, s128}, {s64, s128}});

Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVGISel.td
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Expand Up @@ -96,6 +96,9 @@ def gi_sh2add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<2>">,
def gi_sh3add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<3>">,
GIComplexPatternEquiv<sh3add_uw_op>;

def gi_sexti32 : GIComplexOperandMatcher<s64, "selectSExtBits<32>">,
GIComplexPatternEquiv<sexti32>;

def gi_zexti32 : GIComplexOperandMatcher<s64, "selectZExtBits<32>">,
GIComplexPatternEquiv<zexti32>;
def gi_zexti16 : GIComplexOperandMatcher<s32, "selectZExtBits<16>">,
Expand Down
20 changes: 14 additions & 6 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
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Expand Up @@ -98,11 +98,17 @@ define double @fcvt_d_wu(i32 %a) nounwind {
}

define double @fcvt_d_wu_load(ptr %p) nounwind {
; CHECKIFD-LABEL: fcvt_d_wu_load:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: lw a0, 0(a0)
; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
; CHECKIFD-NEXT: ret
; RV32IFD-LABEL: fcvt_d_wu_load:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lw a0, 0(a0)
; RV32IFD-NEXT: fcvt.d.wu fa0, a0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_d_wu_load:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lwu a0, 0(a0)
; RV64IFD-NEXT: fcvt.d.wu fa0, a0
; RV64IFD-NEXT: ret
%a = load i32, ptr %p
%1 = uitofp i32 %a to double
ret double %1
Expand Down Expand Up @@ -294,7 +300,9 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
; RV64IFD-NEXT: fcvt.d.wu fa5, a0
; RV64IFD-NEXT: slli a2, a0, 32
; RV64IFD-NEXT: srli a2, a2, 32
; RV64IFD-NEXT: fcvt.d.wu fa5, a2
; RV64IFD-NEXT: fsd fa5, 0(a1)
; RV64IFD-NEXT: ret
%3 = add i32 %0, 1
Expand Down
20 changes: 14 additions & 6 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
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Expand Up @@ -101,11 +101,17 @@ define float @fcvt_s_wu(i32 %a) nounwind {
}

define float @fcvt_s_wu_load(ptr %p) nounwind {
; CHECKIF-LABEL: fcvt_s_wu_load:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: lw a0, 0(a0)
; CHECKIF-NEXT: fcvt.s.wu fa0, a0
; CHECKIF-NEXT: ret
; RV32IF-LABEL: fcvt_s_wu_load:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lw a0, 0(a0)
; RV32IF-NEXT: fcvt.s.wu fa0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_wu_load:
; RV64IF: # %bb.0:
; RV64IF-NEXT: lwu a0, 0(a0)
; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
%a = load i32, ptr %p
%1 = uitofp i32 %a to float
ret float %1
Expand Down Expand Up @@ -266,7 +272,9 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
; RV64IF-NEXT: fcvt.s.wu fa5, a0
; RV64IF-NEXT: slli a2, a0, 32
; RV64IF-NEXT: srli a2, a2, 32
; RV64IF-NEXT: fcvt.s.wu fa5, a2
; RV64IF-NEXT: fsw fa5, 0(a1)
; RV64IF-NEXT: ret
%3 = add i32 %0, 1
Expand Down
46 changes: 0 additions & 46 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
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Expand Up @@ -2,52 +2,6 @@
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: sitofp_s64_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: sitofp_s64_s32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
; CHECK-NEXT: PseudoRET implicit $f10_h
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:fprb(s16) = G_SITOFP %1(s32)
$f10_h = COPY %2(s16)
PseudoRET implicit $f10_h

...
---
name: uitofp_s64_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: uitofp_s64_s32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
; CHECK-NEXT: PseudoRET implicit $f10_h
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:fprb(s16) = G_UITOFP %1(s32)
$f10_h = COPY %2(s16)
PseudoRET implicit $f10_h

...
---
name: sitofp_s64_s64
legalized: true
Expand Down
92 changes: 0 additions & 92 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,52 +2,6 @@
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: sitofp_s32_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: sitofp_s32_s32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[COPY]], 7
; CHECK-NEXT: $f10_f = COPY [[FCVT_S_W]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:fprb(s32) = G_SITOFP %1(s32)
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: uitofp_s32_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: uitofp_s32_s32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[FCVT_S_WU:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_WU [[COPY]], 7
; CHECK-NEXT: $f10_f = COPY [[FCVT_S_WU]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:fprb(s32) = G_UITOFP %1(s32)
$f10_f = COPY %2(s32)
PseudoRET implicit $f10_f

...
---
name: sitofp_s32_s64
legalized: true
Expand Down Expand Up @@ -91,52 +45,6 @@ body: |
$f10_f = COPY %1(s32)
PseudoRET implicit $f10_f

...
---
name: sitofp_s64_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: sitofp_s64_s32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_W [[COPY]], 0
; CHECK-NEXT: $f10_d = COPY [[FCVT_D_W]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:fprb(s64) = G_SITOFP %1(s32)
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
---
name: uitofp_s64_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: uitofp_s64_s32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[FCVT_D_WU:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_WU [[COPY]], 0
; CHECK-NEXT: $f10_d = COPY [[FCVT_D_WU]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:gprb(s64) = COPY $x10
%1:gprb(s32) = G_TRUNC %0(s64)
%2:fprb(s64) = G_UITOFP %1(s32)
$f10_d = COPY %2(s64)
PseudoRET implicit $f10_d

...
---
name: sitofp_s64_s64
Expand Down
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