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[RISCV] Enable bidirectional scheduling and tracking register pressure #115445

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Nov 15, 2024
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[RISCV] Enable bidirectional scheduling and tracking register pressure #115445

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13 changes: 13 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSubtarget.cpp
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Expand Up @@ -16,6 +16,7 @@
#include "RISCV.h"
#include "RISCVFrameLowering.h"
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/MC/TargetRegistry.h"
Expand Down Expand Up @@ -199,3 +200,15 @@ unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
? RISCVMinimumJumpTableEntries
: TuneInfo->MinimumJumpTableEntries;
}

void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
unsigned NumRegionInstrs) const {
// Do bidirectional scheduling since it provides a more balanced scheduling
// leading to better performance. This will increase compile time.
Policy.OnlyTopDown = false;
Policy.OnlyBottomUp = false;

// Spilling is generally expensive on all RISC-V cores, so always enable
// register-pressure tracking. This will increase compile time.
Policy.ShouldTrackPressure = true;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSubtarget.h
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Expand Up @@ -327,6 +327,9 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned getTailDupAggressiveThreshold() const {
return TuneInfo->TailDupAggressiveThreshold;
}

void overrideSchedPolicy(MachineSchedPolicy &Policy,
unsigned NumRegionInstrs) const override;
};
} // End llvm namespace

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
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Expand Up @@ -25,17 +25,17 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) {
; RV32IM-LABEL: add_i8_signext_i32:
; RV32IM: # %bb.0: # %entry
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: slli a1, a1, 24
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: srai a1, a1, 24
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64IM-LABEL: add_i8_signext_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: slli a1, a1, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
Expand Down
136 changes: 68 additions & 68 deletions llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
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Expand Up @@ -6,17 +6,17 @@ define i2 @bitreverse_i2(i2 %x) {
; RV32-LABEL: bitreverse_i2:
; RV32: # %bb.0:
; RV32-NEXT: slli a1, a0, 1
; RV32-NEXT: andi a1, a1, 2
; RV32-NEXT: andi a0, a0, 3
; RV32-NEXT: andi a1, a1, 2
; RV32-NEXT: srli a0, a0, 1
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: bitreverse_i2:
; RV64: # %bb.0:
; RV64-NEXT: slli a1, a0, 1
; RV64-NEXT: andi a1, a1, 2
; RV64-NEXT: andi a0, a0, 3
; RV64-NEXT: andi a1, a1, 2
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
Expand All @@ -28,8 +28,8 @@ define i3 @bitreverse_i3(i3 %x) {
; RV32-LABEL: bitreverse_i3:
; RV32: # %bb.0:
; RV32-NEXT: slli a1, a0, 2
; RV32-NEXT: andi a1, a1, 4
; RV32-NEXT: andi a0, a0, 7
; RV32-NEXT: andi a1, a1, 4
; RV32-NEXT: andi a2, a0, 2
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: srli a0, a0, 2
Expand All @@ -39,8 +39,8 @@ define i3 @bitreverse_i3(i3 %x) {
; RV64-LABEL: bitreverse_i3:
; RV64: # %bb.0:
; RV64-NEXT: slli a1, a0, 2
; RV64-NEXT: andi a1, a1, 4
; RV64-NEXT: andi a0, a0, 7
; RV64-NEXT: andi a1, a1, 4
; RV64-NEXT: andi a2, a0, 2
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: srli a0, a0, 2
Expand All @@ -54,11 +54,11 @@ define i4 @bitreverse_i4(i4 %x) {
; RV32-LABEL: bitreverse_i4:
; RV32: # %bb.0:
; RV32-NEXT: slli a1, a0, 3
; RV32-NEXT: andi a1, a1, 8
; RV32-NEXT: slli a2, a0, 1
; RV32-NEXT: andi a0, a0, 15
; RV32-NEXT: andi a1, a1, 8
; RV32-NEXT: andi a2, a2, 4
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: andi a0, a0, 15
; RV32-NEXT: srli a2, a0, 1
; RV32-NEXT: andi a2, a2, 2
; RV32-NEXT: or a1, a1, a2
Expand All @@ -69,11 +69,11 @@ define i4 @bitreverse_i4(i4 %x) {
; RV64-LABEL: bitreverse_i4:
; RV64: # %bb.0:
; RV64-NEXT: slli a1, a0, 3
; RV64-NEXT: andi a1, a1, 8
; RV64-NEXT: slli a2, a0, 1
; RV64-NEXT: andi a0, a0, 15
; RV64-NEXT: andi a1, a1, 8
; RV64-NEXT: andi a2, a2, 4
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: andi a0, a0, 15
; RV64-NEXT: srli a2, a0, 1
; RV64-NEXT: andi a2, a2, 2
; RV64-NEXT: or a1, a1, a2
Expand All @@ -88,21 +88,21 @@ define i7 @bitreverse_i7(i7 %x) {
; RV32-LABEL: bitreverse_i7:
; RV32: # %bb.0:
; RV32-NEXT: slli a1, a0, 6
; RV32-NEXT: andi a1, a1, 64
; RV32-NEXT: slli a2, a0, 4
; RV32-NEXT: slli a3, a0, 2
; RV32-NEXT: andi a0, a0, 127
; RV32-NEXT: andi a1, a1, 64
; RV32-NEXT: andi a2, a2, 32
; RV32-NEXT: andi a3, a3, 16
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: slli a2, a0, 2
; RV32-NEXT: andi a2, a2, 16
; RV32-NEXT: andi a0, a0, 127
; RV32-NEXT: andi a3, a0, 8
; RV32-NEXT: or a2, a2, a3
; RV32-NEXT: andi a2, a0, 8
; RV32-NEXT: or a2, a3, a2
; RV32-NEXT: srli a3, a0, 2
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: srli a2, a0, 2
; RV32-NEXT: andi a2, a2, 4
; RV32-NEXT: srli a3, a0, 4
; RV32-NEXT: andi a3, a3, 2
; RV32-NEXT: or a2, a2, a3
; RV32-NEXT: srli a2, a0, 4
; RV32-NEXT: andi a3, a3, 4
; RV32-NEXT: andi a2, a2, 2
; RV32-NEXT: or a2, a3, a2
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: srli a0, a0, 6
; RV32-NEXT: or a0, a1, a0
Expand All @@ -111,21 +111,21 @@ define i7 @bitreverse_i7(i7 %x) {
; RV64-LABEL: bitreverse_i7:
; RV64: # %bb.0:
; RV64-NEXT: slli a1, a0, 6
; RV64-NEXT: andi a1, a1, 64
; RV64-NEXT: slli a2, a0, 4
; RV64-NEXT: slli a3, a0, 2
; RV64-NEXT: andi a0, a0, 127
; RV64-NEXT: andi a1, a1, 64
; RV64-NEXT: andi a2, a2, 32
; RV64-NEXT: andi a3, a3, 16
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: slli a2, a0, 2
; RV64-NEXT: andi a2, a2, 16
; RV64-NEXT: andi a0, a0, 127
; RV64-NEXT: andi a3, a0, 8
; RV64-NEXT: or a2, a2, a3
; RV64-NEXT: andi a2, a0, 8
; RV64-NEXT: or a2, a3, a2
; RV64-NEXT: srli a3, a0, 2
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: srli a2, a0, 2
; RV64-NEXT: andi a2, a2, 4
; RV64-NEXT: srli a3, a0, 4
; RV64-NEXT: andi a3, a3, 2
; RV64-NEXT: or a2, a2, a3
; RV64-NEXT: srli a2, a0, 4
; RV64-NEXT: andi a3, a3, 4
; RV64-NEXT: andi a2, a2, 2
; RV64-NEXT: or a2, a3, a2
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: srli a0, a0, 6
; RV64-NEXT: or a0, a1, a0
Expand All @@ -139,67 +139,67 @@ define i24 @bitreverse_i24(i24 %x) {
; RV32: # %bb.0:
; RV32-NEXT: slli a1, a0, 16
; RV32-NEXT: lui a2, 4096
; RV32-NEXT: lui a3, 1048335
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: addi a3, a3, 240
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: srli a0, a0, 16
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: lui a1, 1048335
; RV32-NEXT: addi a1, a1, 240
; RV32-NEXT: and a3, a1, a2
; RV32-NEXT: and a3, a0, a3
; RV32-NEXT: srli a3, a3, 4
; RV32-NEXT: and a1, a3, a2
; RV32-NEXT: and a1, a0, a1
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: or a0, a3, a0
; RV32-NEXT: lui a1, 1047757
; RV32-NEXT: addi a1, a1, -820
; RV32-NEXT: and a3, a1, a2
; RV32-NEXT: and a3, a0, a3
; RV32-NEXT: srli a3, a3, 2
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: lui a3, 1047757
; RV32-NEXT: addi a3, a3, -820
; RV32-NEXT: srli a1, a1, 4
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: and a1, a3, a2
; RV32-NEXT: and a1, a0, a1
; RV32-NEXT: slli a0, a0, 2
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: or a0, a3, a0
; RV32-NEXT: lui a1, 1047211
; RV32-NEXT: addi a1, a1, -1366
; RV32-NEXT: and a2, a1, a2
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: lui a3, 1047211
; RV32-NEXT: addi a3, a3, -1366
; RV32-NEXT: and a2, a3, a2
; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: and a2, a0, a2
; RV32-NEXT: srli a2, a2, 1
; RV32-NEXT: slli a0, a0, 1
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: srli a2, a2, 1
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: or a0, a2, a0
; RV32-NEXT: ret
;
; RV64-LABEL: bitreverse_i24:
; RV64: # %bb.0:
; RV64-NEXT: slli a1, a0, 16
; RV64-NEXT: lui a2, 4096
; RV64-NEXT: lui a3, 1048335
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: addiw a3, a3, 240
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: srli a0, a0, 16
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: lui a1, 1048335
; RV64-NEXT: addiw a1, a1, 240
; RV64-NEXT: and a3, a1, a2
; RV64-NEXT: and a3, a0, a3
; RV64-NEXT: srli a3, a3, 4
; RV64-NEXT: and a1, a3, a2
; RV64-NEXT: and a1, a0, a1
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: or a0, a3, a0
; RV64-NEXT: lui a1, 1047757
; RV64-NEXT: addiw a1, a1, -820
; RV64-NEXT: and a3, a1, a2
; RV64-NEXT: and a3, a0, a3
; RV64-NEXT: srli a3, a3, 2
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: lui a3, 1047757
; RV64-NEXT: addiw a3, a3, -820
; RV64-NEXT: srli a1, a1, 4
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: and a1, a3, a2
; RV64-NEXT: and a1, a0, a1
; RV64-NEXT: slli a0, a0, 2
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: or a0, a3, a0
; RV64-NEXT: lui a1, 1047211
; RV64-NEXT: addiw a1, a1, -1366
; RV64-NEXT: and a2, a1, a2
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: lui a3, 1047211
; RV64-NEXT: addiw a3, a3, -1366
; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: and a2, a0, a2
; RV64-NEXT: srli a2, a2, 1
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: srli a2, a2, 1
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: or a0, a2, a0
; RV64-NEXT: ret
%rev = call i24 @llvm.bitreverse.i24(i24 %x)
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
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Expand Up @@ -21,34 +21,34 @@ define void @constant_fold_barrier_i128(ptr %p) {
; RV32-LABEL: constant_fold_barrier_i128:
; RV32: # %bb.0: # %entry
; RV32-NEXT: li a1, 1
; RV32-NEXT: slli a1, a1, 11
; RV32-NEXT: lw a2, 0(a0)
; RV32-NEXT: lw a3, 4(a0)
; RV32-NEXT: lw a4, 8(a0)
; RV32-NEXT: lw a5, 12(a0)
; RV32-NEXT: slli a1, a1, 11
; RV32-NEXT: and a2, a2, a1
; RV32-NEXT: and a3, a3, zero
; RV32-NEXT: and a4, a4, zero
; RV32-NEXT: and a5, a5, zero
; RV32-NEXT: add a2, a2, a1
; RV32-NEXT: sltu a1, a2, a1
; RV32-NEXT: add a6, a3, zero
; RV32-NEXT: sltu a1, a2, a1
; RV32-NEXT: sltu a3, a6, a3
; RV32-NEXT: add a6, a6, a1
; RV32-NEXT: seqz a7, a6
; RV32-NEXT: and a1, a7, a1
; RV32-NEXT: add a7, a4, zero
; RV32-NEXT: add a5, a5, zero
; RV32-NEXT: sltu a4, a7, a4
; RV32-NEXT: or a1, a3, a1
; RV32-NEXT: add a3, a4, zero
; RV32-NEXT: sltu a4, a3, a4
; RV32-NEXT: add a3, a3, a1
; RV32-NEXT: seqz a7, a3
; RV32-NEXT: and a1, a7, a1
; RV32-NEXT: add a7, a7, a1
; RV32-NEXT: seqz a3, a7
; RV32-NEXT: and a1, a3, a1
; RV32-NEXT: or a1, a4, a1
; RV32-NEXT: add a5, a5, zero
; RV32-NEXT: add a1, a5, a1
; RV32-NEXT: sw a2, 0(a0)
; RV32-NEXT: sw a6, 4(a0)
; RV32-NEXT: sw a3, 8(a0)
; RV32-NEXT: sw a7, 8(a0)
; RV32-NEXT: sw a1, 12(a0)
; RV32-NEXT: ret
entry:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv64.ll
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Expand Up @@ -21,9 +21,9 @@ define i128 @constant_fold_barrier_i128(i128 %x) {
; RV64-LABEL: constant_fold_barrier_i128:
; RV64: # %bb.0: # %entry
; RV64-NEXT: li a2, 1
; RV64-NEXT: and a1, a1, zero
; RV64-NEXT: slli a2, a2, 11
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: and a1, a1, zero
; RV64-NEXT: add a0, a0, a2
; RV64-NEXT: sltu a2, a0, a2
; RV64-NEXT: add a1, a1, zero
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
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Expand Up @@ -117,8 +117,8 @@ define i64 @abs64(i64 %x) {
; RV32I: # %bb.0:
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: sltu a3, a0, a2
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: sltu a3, a0, a2
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a1, a1, a2
Expand All @@ -128,8 +128,8 @@ define i64 @abs64(i64 %x) {
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srai a2, a1, 31
; RV32ZBB-NEXT: add a0, a0, a2
; RV32ZBB-NEXT: sltu a3, a0, a2
; RV32ZBB-NEXT: add a1, a1, a2
; RV32ZBB-NEXT: sltu a3, a0, a2
; RV32ZBB-NEXT: add a1, a1, a3
; RV32ZBB-NEXT: xor a0, a0, a2
; RV32ZBB-NEXT: xor a1, a1, a2
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
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Expand Up @@ -302,8 +302,8 @@ define i64 @rori_i64(i64 %a) nounwind {
; CHECK-NEXT: slli a2, a0, 31
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: slli a3, a1, 31
; CHECK-NEXT: or a0, a0, a3
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: or a0, a0, a3
; CHECK-NEXT: or a1, a2, a1
; CHECK-NEXT: ret
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 63)
Expand Down
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