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[SelectionDAG] Add support for extending masked loads in computeKnownBits #115450

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Merged
merged 1 commit into from
Nov 11, 2024
Merged

[SelectionDAG] Add support for extending masked loads in computeKnownBits #115450

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13 changes: 13 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3920,6 +3920,19 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
Known.Zero.setBitsFrom(1);
break;
}
case ISD::MGATHER:
case ISD::MLOAD: {
ISD::LoadExtType ETy =
(Opcode == ISD::MGATHER)
? cast<MaskedGatherSDNode>(Op)->getExtensionType()
: cast<MaskedLoadSDNode>(Op)->getExtensionType();
if (ETy == ISD::ZEXTLOAD) {
EVT MemVT = cast<MemSDNode>(Op)->getMemoryVT();
KnownBits Known0(MemVT.getScalarSizeInBits());
return Known0.zext(BitWidth);
}
break;
}
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Op);
const Constant *Cst = TLI->getTargetConstantFromLoad(LD);
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14 changes: 6 additions & 8 deletions llvm/test/CodeGen/AArch64/sve-hadd.ll
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Expand Up @@ -1347,10 +1347,8 @@ define void @zext_mload_avgflooru(ptr %p1, ptr %p2, <vscale x 8 x i1> %mask) {
; SVE: // %bb.0:
; SVE-NEXT: ld1b { z0.h }, p0/z, [x0]
; SVE-NEXT: ld1b { z1.h }, p0/z, [x1]
; SVE-NEXT: eor z2.d, z0.d, z1.d
; SVE-NEXT: and z0.d, z0.d, z1.d
; SVE-NEXT: lsr z1.h, z2.h, #1
; SVE-NEXT: add z0.h, z0.h, z1.h
; SVE-NEXT: lsr z0.h, z0.h, #1
; SVE-NEXT: st1h { z0.h }, p0, [x0]
; SVE-NEXT: ret
;
Expand All @@ -1377,11 +1375,11 @@ define void @zext_mload_avgceilu(ptr %p1, ptr %p2, <vscale x 8 x i1> %mask) {
; SVE-LABEL: zext_mload_avgceilu:
; SVE: // %bb.0:
; SVE-NEXT: ld1b { z0.h }, p0/z, [x0]
; SVE-NEXT: ld1b { z1.h }, p0/z, [x1]
; SVE-NEXT: eor z2.d, z0.d, z1.d
; SVE-NEXT: orr z0.d, z0.d, z1.d
; SVE-NEXT: lsr z1.h, z2.h, #1
; SVE-NEXT: sub z0.h, z0.h, z1.h
; SVE-NEXT: mov z1.h, #-1 // =0xffffffffffffffff
; SVE-NEXT: ld1b { z2.h }, p0/z, [x1]
; SVE-NEXT: eor z0.d, z0.d, z1.d
; SVE-NEXT: sub z0.h, z2.h, z0.h
; SVE-NEXT: lsr z0.h, z0.h, #1
; SVE-NEXT: st1b { z0.h }, p0, [x0]
; SVE-NEXT: ret
;
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