[AMDGPU] Reorganize tests to unblock #112403 #115503

shiltian · 2024-11-08T16:00:41Z

We’re facing an issue (#113782) that is currently blocking #112403. However,
since #112403 involves extensive test changes, I’d prefer to land it as soon as
possible. This PR reorganizes the tests by moving test cases expected to fail
into a separate file. Additionally, it changes the [15 x i32] arguments to
[13 x i32] to bypass the issue.

shiltian · 2024-11-08T16:00:57Z

[AMDGPU] Reorganize tests to unblock #112403 #115503 : 2 dependent PRs (#112403 , #115505 ) 👈
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llvmbot · 2024-11-08T16:01:18Z

@llvm/pr-subscribers-backend-amdgpu

Author: Shilei Tian (shiltian)

Changes

We’re facing an issue (#113782) that is currently blocking #112403. However,
since #112403 involves extensive test changes, I’d prefer to land it as soon as
possible. This PR reorganizes the tests by moving test cases expected to fail
into a separate file. Additionally, it changes the [15 x i32] arguments to
[13 x i32] to bypass the issue.

Full diff: https://github.com/llvm/llvm-project/pull/115503.diff

2 Files Affected:

(added) llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll (+36)
(modified) llvm/test/CodeGen/AMDGPU/call-args-inreg.ll (+39-65)

diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
new file mode 100644
index 00000000000000..47c53fcae6a0bf
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s
+
+; XFAIL: *
+
+declare hidden void @external_void_func_a15i32_inreg([15 x i32] inreg) #0
+declare hidden void @external_void_func_a16i32_inreg([16 x i32] inreg) #0
+declare hidden void @external_void_func_a15i32_inreg_i32_inreg([15 x i32] inreg, i32 inreg) #0
+declare hidden void @external_void_func_a15i32_inreg_i32_inreg__noimplicit([15 x i32] inreg, i32 inreg) #1
+
+define void @test_call_external_void_func_a15i32_inreg([15 x i32] inreg %arg0) #0 {
+  call void @external_void_func_a15i32_inreg([15 x i32] inreg %arg0)
+  ret void
+}
+
+define void @test_call_external_void_func_a16i32_inreg([16 x i32] inreg %arg0) #0 {
+  call void @external_void_func_a16i32_inreg([16 x i32] inreg %arg0)
+  ret void
+}
+
+define void @test_call_external_void_func_a15i32_inreg_i32_inreg([15 x i32] inreg %arg0, i32 inreg %arg1) #0 {
+  call void @external_void_func_a15i32_inreg_i32_inreg([15 x i32] inreg %arg0, i32 inreg %arg1)
+  ret void
+}
+
+
+define void @test_call_external_void_func_a15i32_inreg_i32_inreg([15 x i32] inreg %arg0, i32 inreg %arg1) #1 {
+  call void @external_void_func_a15i32_inreg_i32_inreg__noimplicit([15 x i32] inreg %arg0, i32 inreg %arg1)
+  ret void
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-work-group-id-x" "amdgpu-no-work-group-id-y" "amdgpu-no-work-group-id-z" "amdgpu-no-work-item-id-x" "amdgpu-no-work-item-id-y" "amdgpu-no-work-item-id-z" }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
index 8766303d7ee6ec..d35b5fe818bef8 100644
--- a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
@@ -28,10 +28,8 @@ declare hidden void @external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inreg)
 
 declare hidden void @external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inreg, i32 inreg, i64 inreg) #0
 
-declare hidden void @external_void_func_a15i32_inreg([15 x i32] inreg) #0
-declare hidden void @external_void_func_a16i32_inreg([16 x i32] inreg) #0
-declare hidden void @external_void_func_a15i32_inreg_i32_inreg([15 x i32] inreg, i32 inreg) #0
-declare hidden void @external_void_func_a15i32_inreg_i32_inreg__noimplicit([15 x i32] inreg, i32 inreg) #1
+declare hidden void @external_void_func_a15i32_inreg([13 x i32] inreg) #0
+declare hidden void @external_void_func_a15i32_inreg_i32_inreg__noimplicit([13 x i32] inreg, i32 inreg) #1
 
 define void @test_call_external_void_func_i8_inreg(i8 inreg %arg) #0 {
 ; GFX9-LABEL: test_call_external_void_func_i8_inreg:
@@ -534,12 +532,6 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 {
   ret void
 }
 
-; FIXME:
-; define void @test_call_external_void_func_v16i32_inreg(<16 x i32> inreg %arg) #0 {
-;   call void @external_void_func_v16i32_inreg(<16 x i32> inreg %arg)
-;   ret void
-; }
-
 define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
 ; GFX9-LABEL: test_call_external_void_func_f16_inreg:
 ; GFX9:       ; %bb.0:
@@ -1402,16 +1394,16 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre
   ret void
 }
 
-define void @test_call_external_void_func_a15i32_inreg([15 x i32] inreg %arg0) #0 {
+define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) #0 {
 ; GFX9-LABEL: test_call_external_void_func_a15i32_inreg:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_mov_b32 s29, s33
+; GFX9-NEXT:    s_mov_b32 s27, s33
 ; GFX9-NEXT:    s_mov_b32 s33, s32
-; GFX9-NEXT:    s_or_saveexec_b64 vcc, -1
+; GFX9-NEXT:    s_or_saveexec_b64 s[28:29], -1
 ; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT:    s_mov_b64 exec, vcc
-; GFX9-NEXT:    v_writelane_b32 v40, s29, 2
+; GFX9-NEXT:    s_mov_b64 exec, s[28:29]
+; GFX9-NEXT:    v_writelane_b32 v40, s27, 2
 ; GFX9-NEXT:    s_addk_i32 s32, 0x400
 ; GFX9-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX9-NEXT:    s_mov_b32 s3, s17
@@ -1427,13 +1419,11 @@ define void @test_call_external_void_func_a15i32_inreg([15 x i32] inreg %arg0) #
 ; GFX9-NEXT:    s_mov_b32 s22, s24
 ; GFX9-NEXT:    s_mov_b32 s23, s25
 ; GFX9-NEXT:    s_mov_b32 s24, s26
-; GFX9-NEXT:    s_mov_b32 s25, s27
-; GFX9-NEXT:    s_mov_b32 s26, s28
 ; GFX9-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX9-NEXT:    s_getpc_b64 vcc
-; GFX9-NEXT:    s_add_u32 vcc_lo, vcc_lo, external_void_func_a15i32_inreg@rel32@lo+4
-; GFX9-NEXT:    s_addc_u32 vcc_hi, vcc_hi, external_void_func_a15i32_inreg@rel32@hi+12
-; GFX9-NEXT:    s_swappc_b64 s[30:31], vcc
+; GFX9-NEXT:    s_getpc_b64 s[28:29]
+; GFX9-NEXT:    s_add_u32 s28, s28, external_void_func_a15i32_inreg@rel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s29, s29, external_void_func_a15i32_inreg@rel32@hi+12
+; GFX9-NEXT:    s_swappc_b64 s[30:31], s[28:29]
 ; GFX9-NEXT:    v_readlane_b32 s31, v40, 1
 ; GFX9-NEXT:    v_readlane_b32 s30, v40, 0
 ; GFX9-NEXT:    v_readlane_b32 s4, v40, 2
@@ -1448,19 +1438,17 @@ define void @test_call_external_void_func_a15i32_inreg([15 x i32] inreg %arg0) #
 ; GFX11-LABEL: test_call_external_void_func_a15i32_inreg:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s25, s33
+; GFX11-NEXT:    s_mov_b32 s23, s33
 ; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s26, -1
+; GFX11-NEXT:    s_or_saveexec_b32 s24, -1
 ; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s26
-; GFX11-NEXT:    v_writelane_b32 v40, s25, 2
-; GFX11-NEXT:    s_mov_b32 s26, s24
-; GFX11-NEXT:    s_mov_b32 s25, s23
+; GFX11-NEXT:    s_mov_b32 exec_lo, s24
+; GFX11-NEXT:    v_writelane_b32 v40, s23, 2
 ; GFX11-NEXT:    s_mov_b32 s24, s22
 ; GFX11-NEXT:    s_mov_b32 s23, s21
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX11-NEXT:    s_mov_b32 s22, s20
 ; GFX11-NEXT:    s_mov_b32 s21, s19
+; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX11-NEXT:    s_mov_b32 s20, s18
 ; GFX11-NEXT:    s_mov_b32 s19, s17
 ; GFX11-NEXT:    s_mov_b32 s18, s16
@@ -1468,11 +1456,11 @@ define void @test_call_external_void_func_a15i32_inreg([15 x i32] inreg %arg0) #
 ; GFX11-NEXT:    s_mov_b32 s16, s6
 ; GFX11-NEXT:    s_add_i32 s32, s32, 16
 ; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_getpc_b64 s[28:29]
-; GFX11-NEXT:    s_add_u32 s28, s28, external_void_func_a15i32_inreg@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s29, s29, external_void_func_a15i32_inreg@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[26:27]
+; GFX11-NEXT:    s_add_u32 s26, s26, external_void_func_a15i32_inreg@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s27, s27, external_void_func_a15i32_inreg@rel32@hi+12
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[28:29]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[26:27]
 ; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
 ; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
 ; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
@@ -1483,34 +1471,22 @@ define void @test_call_external_void_func_a15i32_inreg([15 x i32] inreg %arg0) #
 ; GFX11-NEXT:    s_mov_b32 s33, s0
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  call void @external_void_func_a15i32_inreg([15 x i32] inreg %arg0)
+  call void @external_void_func_a15i32_inreg([13 x i32] inreg %arg0)
   ret void
 }
 
-; FIXME:
-; define void @test_call_external_void_func_a16i32_inreg([16 x i32] inreg %arg0) #0 {
-;   call void @external_void_func_a16i32_inreg([16 x i32] inreg %arg0)
-;   ret void
-; }
-
-; FIXME:
-; define void @test_call_external_void_func_a15i32_inreg_i32_inreg([15 x i32] inreg %arg0, i32 inreg %arg1) #0 {
-;   call void @external_void_func_a15i32_inreg_i32_inreg([15 x i32] inreg %arg0, i32 inreg %arg1)
-;   ret void
-; }
-
 
 ; FIXME: This should also fail
-define void @test_call_external_void_func_a15i32_inreg_i32_inreg([15 x i32] inreg %arg0, i32 inreg %arg1) #1 {
+define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inreg %arg0, i32 inreg %arg1) #1 {
 ; GFX9-LABEL: test_call_external_void_func_a15i32_inreg_i32_inreg:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_mov_b32 s23, s33
+; GFX9-NEXT:    s_mov_b32 s21, s33
 ; GFX9-NEXT:    s_mov_b32 s33, s32
-; GFX9-NEXT:    s_or_saveexec_b64 s[24:25], -1
+; GFX9-NEXT:    s_or_saveexec_b64 s[22:23], -1
 ; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT:    s_mov_b64 exec, s[24:25]
-; GFX9-NEXT:    v_writelane_b32 v40, s23, 2
+; GFX9-NEXT:    s_mov_b64 exec, s[22:23]
+; GFX9-NEXT:    v_writelane_b32 v40, s21, 2
 ; GFX9-NEXT:    s_addk_i32 s32, 0x400
 ; GFX9-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX9-NEXT:    s_mov_b32 s3, s7
@@ -1527,13 +1503,11 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([15 x i32] inre
 ; GFX9-NEXT:    s_mov_b32 s11, s18
 ; GFX9-NEXT:    s_mov_b32 s15, s19
 ; GFX9-NEXT:    s_mov_b32 s16, s20
-; GFX9-NEXT:    s_mov_b32 s17, s21
-; GFX9-NEXT:    s_mov_b32 s18, s22
 ; GFX9-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX9-NEXT:    s_getpc_b64 s[24:25]
-; GFX9-NEXT:    s_add_u32 s24, s24, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@lo+4
-; GFX9-NEXT:    s_addc_u32 s25, s25, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@hi+12
-; GFX9-NEXT:    s_swappc_b64 s[30:31], s[24:25]
+; GFX9-NEXT:    s_getpc_b64 s[22:23]
+; GFX9-NEXT:    s_add_u32 s22, s22, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@lo+4
+; GFX9-NEXT:    s_addc_u32 s23, s23, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@hi+12
+; GFX9-NEXT:    s_swappc_b64 s[30:31], s[22:23]
 ; GFX9-NEXT:    v_readlane_b32 s31, v40, 1
 ; GFX9-NEXT:    v_readlane_b32 s30, v40, 0
 ; GFX9-NEXT:    v_readlane_b32 s4, v40, 2
@@ -1548,19 +1522,19 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([15 x i32] inre
 ; GFX11-LABEL: test_call_external_void_func_a15i32_inreg_i32_inreg:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s19, s33
+; GFX11-NEXT:    s_mov_b32 s17, s33
 ; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s20, -1
+; GFX11-NEXT:    s_or_saveexec_b32 s18, -1
 ; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s20
-; GFX11-NEXT:    v_writelane_b32 v40, s19, 2
+; GFX11-NEXT:    s_mov_b32 exec_lo, s18
+; GFX11-NEXT:    v_writelane_b32 v40, s17, 2
 ; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    s_getpc_b64 s[20:21]
-; GFX11-NEXT:    s_add_u32 s20, s20, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s21, s21, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@hi+12
+; GFX11-NEXT:    s_getpc_b64 s[18:19]
+; GFX11-NEXT:    s_add_u32 s18, s18, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@lo+4
+; GFX11-NEXT:    s_addc_u32 s19, s19, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@hi+12
 ; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[20:21]
+; GFX11-NEXT:    s_swappc_b64 s[30:31], s[18:19]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
 ; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
@@ -1572,7 +1546,7 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([15 x i32] inre
 ; GFX11-NEXT:    s_mov_b32 s33, s0
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  call void @external_void_func_a15i32_inreg_i32_inreg__noimplicit([15 x i32] inreg %arg0, i32 inreg %arg1)
+  call void @external_void_func_a15i32_inreg_i32_inreg__noimplicit([13 x i32] inreg %arg0, i32 inreg %arg1)
   ret void
 }

llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll

shiltian · 2024-11-08T16:02:11Z

llvm/test/CodeGen/AMDGPU/call-args-inreg.ll

  ret void
 }

-; FIXME:


These FIXME has been moved to the new file.

llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll

arsenm · 2024-11-08T16:02:36Z

llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll

+attributes #0 = { nounwind }
+attributes #1 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-work-group-id-x" "amdgpu-no-work-group-id-y" "amdgpu-no-work-group-id-z" "amdgpu-no-work-item-id-x" "amdgpu-no-work-item-id-y" "amdgpu-no-work-item-id-z" }
+
+!llvm.module.flags = !{!0}


Also should migrate to v5?

I intentionally make it as 400 because this can expose the issue.

so both [16 x i32] in COV5 and [15 x i32] in COV4 can expose the issue.

llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll

shiltian · 2024-11-08T17:54:20Z

Merge activity

Nov 8, 12:54 PM EST: A user started a stack merge that includes this pull request via Graphite.
Nov 8, 12:58 PM EST: Graphite rebased this pull request as part of a merge.
Nov 8, 1:00 PM EST: A user merged this pull request with Graphite.
Nov 8, 1:03 PM EST: A user started a stack merge that includes this pull request via Graphite.

We’re facing an issue (#113782) that is currently blocking #112403. However, since #112403 involves extensive test changes, I’d prefer to land it as soon as possible. This PR reorganizes the tests by moving test cases expected to fail into a separate file. Additionally, it changes the `[15 x i32]` arguments to `[13 x i32]` to bypass the issue.

llvm-ci · 2024-11-08T21:49:54Z

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-expensive-checks-debian running on gribozavr4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/8546

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 1: not --crash /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll -filetype=null 2>&1 | /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck -enable-var-scope /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
+ not --crash /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll -filetype=null
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck -enable-var-scope /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
/b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll:3:10: error: CHECK: expected string not found in input
; CHECK: LLVM ERROR: failed to find free scratch register
         ^
<stdin>:1:1: note: scanning from here

^
<stdin>:2:14: note: possible intended match here
# After Eliminate PHI nodes for register allocation
             ^

Input file: <stdin>
Check file: /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
           1:  
check:3'0     X error: no match found
           2: # After Eliminate PHI nodes for register allocation 
check:3'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
check:3'1                  ?                                       possible intended match
           3: # Machine code for function test_call_external_void_func_a15i32_inreg: NoPHIs, TracksLiveness 
check:3'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           4: Function Live Ins: $sgpr4_sgpr5 in %0, $sgpr6_sgpr7 in %1, $sgpr8_sgpr9 in %2, $sgpr10_sgpr11 in %3, $sgpr12 in %4, $sgpr13 in %5, $sgpr14 in %6, $sgpr15 in %7, $sgpr16 in %8, $sgpr17 in %9, $sgpr18 in %10, $sgpr19 in %11, $sgpr20 in %12, $sgpr21 in %13, $sgpr22 in %14, $sgpr23 in %15, $sgpr24 in %16, $sgpr25 in %17, $sgpr26 in %18, $sgpr27 in %19, $sgpr28 in %20, $sgpr29 in %21, $vgpr0 in %22, $vgpr31 in %23 
check:3'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           5:  
check:3'0     ~
           6: bb.0 (%ir-block.0): 
check:3'0     ~~~~~~~~~~~~~~~~~~~~
           7:  liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $vgpr0, $vgpr31 
check:3'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           .
           .
           .
>>>>>>

--

********************

We’re facing an issue (llvm#113782) that is currently blocking llvm#112403. However, since llvm#112403 involves extensive test changes, I’d prefer to land it as soon as possible. This PR reorganizes the tests by moving test cases expected to fail into a separate file. Additionally, it changes the `[15 x i32]` arguments to `[13 x i32]` to bypass the issue.

llvmbot added the backend:AMDGPU label Nov 8, 2024

shiltian mentioned this pull request Nov 8, 2024

[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 #112403

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shiltian requested a review from arsenm November 8, 2024 16:01

shiltian commented Nov 8, 2024

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shiltian commented Nov 8, 2024

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llvm/test/CodeGen/AMDGPU/call-args-inreg.ll

ret void

}

; FIXME:

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These FIXME has been moved to the new file.

arsenm reviewed Nov 8, 2024

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arsenm reviewed Nov 8, 2024

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shiltian force-pushed the users/shiltian/disable-test-no-sgpr-for-csrspill branch from 803a03c to 737d4f1 Compare November 8, 2024 16:08

shiltian mentioned this pull request Nov 8, 2024

[AMDGPU] Fix #115505

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arsenm reviewed Nov 8, 2024

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shiltian force-pushed the users/shiltian/disable-test-no-sgpr-for-csrspill branch from 737d4f1 to 9b97b93 Compare November 8, 2024 16:16

arsenm approved these changes Nov 8, 2024

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shiltian force-pushed the users/shiltian/disable-test-no-sgpr-for-csrspill branch from 9b97b93 to b289eef Compare November 8, 2024 17:57

shiltian merged commit d30a6dc into main Nov 8, 2024
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shiltian deleted the users/shiltian/disable-test-no-sgpr-for-csrspill branch November 8, 2024 18:00

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