[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. #115559
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Still to add custom isel to select SRAIW+SRLIW like SelectionDAG.
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@llvm/pr-subscribers-llvm-globalisel Author: Craig Topper (topperc) ChangesUnless the shift amount is constant. In that case we zero extend the shift amount and promote the other input the same way widenScalar would. I'm not using widenScalar because that requires a separate call for each operand so it was easier to do both operands at once. Patch is 203.34 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/115559.diff 27 Files Affected:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 91353772e201ef..c9ac45ac3519e7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -159,12 +159,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.lower();
getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
- .legalFor({{s32, s32}, {sXLen, sXLen}})
+ .legalFor({{sXLen, sXLen}})
+ .customFor(ST.is64Bit(), {{s32, s32}})
.widenScalarToNextPow2(0)
- .clampScalar(1, s32, sXLen)
- .clampScalar(0, s32, sXLen)
- .minScalarSameAs(1, 0)
- .maxScalarSameAs(1, 0);
+ .clampScalar(1, sXLen, sXLen)
+ .clampScalar(0, sXLen, sXLen);
auto &ExtActions =
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
@@ -1171,6 +1170,12 @@ static unsigned getRISCVWOpcode(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unexpected opcode");
+ case TargetOpcode::G_ASHR:
+ return RISCV::G_SRAW;
+ case TargetOpcode::G_LSHR:
+ return RISCV::G_SRLW;
+ case TargetOpcode::G_SHL:
+ return RISCV::G_SLLW;
case TargetOpcode::G_SDIV:
return RISCV::G_DIVW;
case TargetOpcode::G_UDIV:
@@ -1228,6 +1233,36 @@ bool RISCVLegalizerInfo::legalizeCustom(
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
LegalizerHelper::Legalized;
}
+ case TargetOpcode::G_ASHR:
+ case TargetOpcode::G_LSHR:
+ case TargetOpcode::G_SHL: {
+ Register AmtReg = MI.getOperand(2).getReg();
+ auto VRegAndVal = getIConstantVRegValWithLookThrough(AmtReg, MRI);
+ if (VRegAndVal) {
+ // We don't need a custom node for shift by constant. Just widen the
+ // source and the shift amount.
+ unsigned ExtOpc = TargetOpcode::G_ANYEXT;
+ if (MI.getOpcode() == TargetOpcode::G_ASHR)
+ ExtOpc = TargetOpcode::G_SEXT;
+ else if (MI.getOpcode() == TargetOpcode::G_LSHR)
+ ExtOpc = TargetOpcode::G_ZEXT;
+
+ Helper.Observer.changingInstr(MI);
+ Helper.widenScalarSrc(MI, sXLen, 1, ExtOpc);
+ Helper.widenScalarSrc(MI, sXLen, 2, TargetOpcode::G_ZEXT);
+ Helper.widenScalarDst(MI, sXLen);
+ Helper.Observer.changedInstr(MI);
+ return true;
+ }
+
+ Helper.Observer.changingInstr(MI);
+ Helper.widenScalarSrc(MI, sXLen, 1, TargetOpcode::G_ANYEXT);
+ Helper.widenScalarSrc(MI, sXLen, 2, TargetOpcode::G_ANYEXT);
+ Helper.widenScalarDst(MI, sXLen);
+ MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode())));
+ Helper.Observer.changedInstr(MI);
+ return true;
+ }
case TargetOpcode::G_SDIV:
case TargetOpcode::G_UDIV:
case TargetOpcode::G_UREM:
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index c0af1d60cb6015..08703411f126ac 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -169,6 +169,15 @@ def : LdPat<load, LD, PtrVT>;
def : StPat<store, SD, GPR, PtrVT>;
}
+let Predicates = [IsRV64] in {
+// FIXME: tblgen can't import sext_inreg patterns.
+def : Pat<(sra (sexti32 (i64 GPR:$rs1)), uimm5:$shamt),
+ (SRAIW GPR:$rs1, uimm5:$shamt)>;
+// FIXME: Temporary until i32->i64 zext is no longer legal.
+def : Pat <(srl (zext GPR:$rs1), uimm5:$shamt),
+ (SRLIW GPR:$rs1, uimm5:$shamt)>;
+}
+
//===----------------------------------------------------------------------===//
// RV64 i32 patterns not used by SelectionDAG
//===----------------------------------------------------------------------===//
@@ -201,9 +210,6 @@ def : PatGprGpr<sub, SUBW, i32, i32>;
def : PatGprGpr<and, AND, i32, i32>;
def : PatGprGpr<or, OR, i32, i32>;
def : PatGprGpr<xor, XOR, i32, i32>;
-def : PatGprGpr<shl, SLLW, i32, i32>;
-def : PatGprGpr<srl, SRLW, i32, i32>;
-def : PatGprGpr<sra, SRAW, i32, i32>;
def : Pat<(i32 (add GPR:$rs1, simm12i32:$imm)),
(ADDIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
@@ -214,13 +220,6 @@ def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
(XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
-def : Pat<(i32 (shl GPR:$rs1, uimm5i32:$imm)),
- (SLLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
-def : Pat<(i32 (srl GPR:$rs1, uimm5i32:$imm)),
- (SRLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
-def : Pat<(i32 (sra GPR:$rs1, uimm5i32:$imm)),
- (SRAIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
-
def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
(SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
(i64 (XLenSubTrailingOnes $mask)))>;
@@ -270,10 +269,4 @@ def : Pat<(shl (i64 (zext i32:$rs1)), uimm5:$shamt),
def : Pat<(i64 (add_like_non_imm12 (zext GPR:$rs1), GPR:$rs2)),
(ADD_UW GPR:$rs1, GPR:$rs2)>;
def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
-
-foreach i = {1,2,3} in {
- defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
- def : Pat<(i32 (add_like_non_imm12 (shl GPR:$rs1, (i32 i)), GPR:$rs2)),
- (shxadd GPR:$rs1, GPR:$rs2)>;
-}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
index bf2f8663cfa156..ac5f4f0ca6cc5b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
@@ -17,6 +17,30 @@ class RISCVGenericInstruction : GenericInstruction {
let Namespace = "RISCV";
}
+// Pseudo equivalent to a RISCVISD::SRAW.
+def G_SRAW : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_SRAW, riscv_sraw>;
+
+// Pseudo equivalent to a RISCVISD::SRLW.
+def G_SRLW : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_SRLW, riscv_srlw>;
+
+// Pseudo equivalent to a RISCVISD::SLLW.
+def G_SLLW : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_SLLW, riscv_sllw>;
+
// Pseudo equivalent to a RISCVISD::DIVW.
def G_DIVW : RISCVGenericInstruction {
let OutOperandList = (outs type0:$dst);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
index 14ff9e01ab3bc2..30560693e8b9fd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
@@ -168,7 +168,7 @@ define i32 @slli_i32(i32 %a) {
;
; RV64IM-LABEL: slli_i32:
; RV64IM: # %bb.0: # %entry
-; RV64IM-NEXT: slliw a0, a0, 11
+; RV64IM-NEXT: slli a0, a0, 11
; RV64IM-NEXT: ret
entry:
%0 = shl i32 %a, 11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
index 5c42fefb95b39f..4c65ee94651029 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
@@ -17,7 +17,7 @@ define i2 @bitreverse_i2(i2 %x) {
; RV64-NEXT: slli a1, a0, 1
; RV64-NEXT: andi a1, a1, 2
; RV64-NEXT: andi a0, a0, 3
-; RV64-NEXT: srliw a0, a0, 1
+; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i2 @llvm.bitreverse.i2(i2 %x)
@@ -43,7 +43,7 @@ define i3 @bitreverse_i3(i3 %x) {
; RV64-NEXT: andi a0, a0, 7
; RV64-NEXT: andi a2, a0, 2
; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: srliw a0, a0, 2
+; RV64-NEXT: srli a0, a0, 2
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i3 @llvm.bitreverse.i3(i3 %x)
@@ -74,10 +74,10 @@ define i4 @bitreverse_i4(i4 %x) {
; RV64-NEXT: andi a2, a2, 4
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: andi a0, a0, 15
-; RV64-NEXT: srliw a2, a0, 1
+; RV64-NEXT: srli a2, a0, 1
; RV64-NEXT: andi a2, a2, 2
; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: srliw a0, a0, 3
+; RV64-NEXT: srli a0, a0, 3
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i4 @llvm.bitreverse.i4(i4 %x)
@@ -121,13 +121,13 @@ define i7 @bitreverse_i7(i7 %x) {
; RV64-NEXT: andi a3, a0, 8
; RV64-NEXT: or a2, a2, a3
; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: srliw a2, a0, 2
+; RV64-NEXT: srli a2, a0, 2
; RV64-NEXT: andi a2, a2, 4
-; RV64-NEXT: srliw a3, a0, 4
+; RV64-NEXT: srli a3, a0, 4
; RV64-NEXT: andi a3, a3, 2
; RV64-NEXT: or a2, a2, a3
; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: srliw a0, a0, 6
+; RV64-NEXT: srli a0, a0, 6
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i7 @llvm.bitreverse.i7(i7 %x)
@@ -171,36 +171,36 @@ define i24 @bitreverse_i24(i24 %x) {
;
; RV64-LABEL: bitreverse_i24:
; RV64: # %bb.0:
-; RV64-NEXT: slli a1, a0, 16
-; RV64-NEXT: lui a2, 4096
-; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: srliw a0, a0, 16
-; RV64-NEXT: or a0, a0, a1
-; RV64-NEXT: lui a1, 1048335
-; RV64-NEXT: addi a1, a1, 240
-; RV64-NEXT: and a3, a1, a2
+; RV64-NEXT: lui a1, 4096
+; RV64-NEXT: addiw a1, a1, -1
+; RV64-NEXT: slli a2, a0, 16
+; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: srli a0, a0, 16
+; RV64-NEXT: or a0, a0, a2
+; RV64-NEXT: lui a2, 1048335
+; RV64-NEXT: addiw a2, a2, 240
+; RV64-NEXT: and a3, a2, a1
; RV64-NEXT: and a3, a0, a3
-; RV64-NEXT: srliw a3, a3, 4
+; RV64-NEXT: srli a3, a3, 4
; RV64-NEXT: slli a0, a0, 4
-; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: or a0, a3, a0
-; RV64-NEXT: lui a1, 1047757
-; RV64-NEXT: addi a1, a1, -820
-; RV64-NEXT: and a3, a1, a2
+; RV64-NEXT: lui a2, 1047757
+; RV64-NEXT: addiw a2, a2, -820
+; RV64-NEXT: and a3, a2, a1
; RV64-NEXT: and a3, a0, a3
-; RV64-NEXT: srliw a3, a3, 2
+; RV64-NEXT: srli a3, a3, 2
; RV64-NEXT: slli a0, a0, 2
-; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: or a0, a3, a0
-; RV64-NEXT: lui a1, 1047211
-; RV64-NEXT: addiw a1, a1, -1366
-; RV64-NEXT: and a2, a1, a2
-; RV64-NEXT: and a2, a0, a2
-; RV64-NEXT: srliw a2, a2, 1
-; RV64-NEXT: slliw a0, a0, 1
-; RV64-NEXT: and a0, a0, a1
-; RV64-NEXT: or a0, a2, a0
+; RV64-NEXT: lui a2, 1047211
+; RV64-NEXT: addiw a2, a2, -1366
+; RV64-NEXT: and a1, a2, a1
+; RV64-NEXT: and a1, a0, a1
+; RV64-NEXT: srli a1, a1, 1
+; RV64-NEXT: slli a0, a0, 1
+; RV64-NEXT: and a0, a0, a2
+; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i24 @llvm.bitreverse.i24(i24 %x)
ret i24 %rev
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
index 6bdc7ce0249197..9093e625d8e429 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
@@ -42,10 +42,18 @@ define i32 @mul_to_shift(i32 %x) {
; RV32-NEXT: slli a0, a0, 2
; RV32-NEXT: ret
;
-; RV64-LABEL: mul_to_shift:
-; RV64: # %bb.0:
-; RV64-NEXT: slliw a0, a0, 2
-; RV64-NEXT: ret
+; RV64-O0-LABEL: mul_to_shift:
+; RV64-O0: # %bb.0:
+; RV64-O0-NEXT: li a1, 2
+; RV64-O0-NEXT: sll a0, a0, a1
+; RV64-O0-NEXT: ret
+;
+; RV64-OPT-LABEL: mul_to_shift:
+; RV64-OPT: # %bb.0:
+; RV64-OPT-NEXT: slli a0, a0, 2
+; RV64-OPT-NEXT: ret
%a = mul i32 %x, 4
ret i32 %a
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
index 32593a74d307ef..7ba3fb055ca1eb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
@@ -32,9 +32,9 @@ define i8 @abs8(i8 %x) {
;
; RV64I-LABEL: abs8:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 24
-; RV64I-NEXT: sraiw a1, a1, 24
-; RV64I-NEXT: sraiw a1, a1, 7
+; RV64I-NEXT: slli a1, a0, 56
+; RV64I-NEXT: srai a1, a1, 56
+; RV64I-NEXT: srai a1, a1, 7
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
@@ -68,9 +68,9 @@ define i16 @abs16(i16 %x) {
;
; RV64I-LABEL: abs16:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: sraiw a1, a1, 16
-; RV64I-NEXT: sraiw a1, a1, 15
+; RV64I-NEXT: slli a1, a0, 48
+; RV64I-NEXT: srai a1, a1, 48
+; RV64I-NEXT: srai a1, a1, 15
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
index 527036d8b750fc..f896ee934fc8c0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
@@ -219,12 +219,9 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SLLW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s64) = COPY $x11
- %3:gprb(s32) = G_TRUNC %2(s64)
- %4:gprb(s32) = G_SHL %1, %3(s32)
- %5:gprb(s64) = G_ANYEXT %4(s32)
- $x10 = COPY %5(s64)
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_SLLW %0, %1
+ $x10 = COPY %2(s64)
PseudoRET implicit $x10
...
@@ -241,15 +238,13 @@ body: |
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; RV64I-NEXT: [[SLLIW:%[0-9]+]]:gpr = SLLIW [[COPY]], 31
- ; RV64I-NEXT: $x10 = COPY [[SLLIW]]
+ ; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31
+ ; RV64I-NEXT: $x10 = COPY [[SLLI]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s32) = G_CONSTANT i32 31
- %3:gprb(s32) = G_SHL %1, %2
- %4:gprb(s64) = G_ANYEXT %3(s32)
- $x10 = COPY %4(s64)
+ %1:gprb(s64) = G_CONSTANT i64 31
+ %2:gprb(s64) = G_SHL %0, %1
+ $x10 = COPY %2(s64)
PseudoRET implicit $x10
...
@@ -271,12 +266,9 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SRAW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s64) = COPY $x11
- %3:gprb(s32) = G_TRUNC %2(s64)
- %4:gprb(s32) = G_ASHR %1, %3(s32)
- %5:gprb(s64) = G_ANYEXT %4(s32)
- $x10 = COPY %5(s64)
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_SRAW %0, %1
+ $x10 = COPY %2(s64)
PseudoRET implicit $x10
...
@@ -297,11 +289,10 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SRAIW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s32) = G_CONSTANT i32 31
- %3:gprb(s32) = G_ASHR %1, %2
- %4:gprb(s64) = G_ANYEXT %3(s32)
- $x10 = COPY %4(s64)
+ %1:gprb(s64) = G_CONSTANT i64 31
+ %2:gprb(s64) = G_SEXT_INREG %0, 32
+ %3:gprb(s64) = G_ASHR %2, %1(s64)
+ $x10 = COPY %3(s64)
PseudoRET implicit $x10
...
@@ -323,12 +314,9 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SRLW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s64) = COPY $x11
- %3:gprb(s32) = G_TRUNC %2(s64)
- %4:gprb(s32) = G_LSHR %1, %3(s32)
- %5:gprb(s64) = G_ANYEXT %4(s32)
- $x10 = COPY %5(s64)
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_SRLW %0, %1
+ $x10 = COPY %2(s64)
PseudoRET implicit $x10
...
@@ -349,10 +337,10 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SRLIW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s32) = G_CONSTANT i32 31
- %3:gprb(s32) = G_LSHR %1, %2
- %4:gprb(s64) = G_ANYEXT %3(s32)
+ %1:gprb(s64) = G_CONSTANT i64 31
+ %2:gprb(s64) = G_CONSTANT i64 4294967295
+ %3:gprb(s64) = G_AND %0, %2
+ %4:gprb(s64) = G_LSHR %3, %1(s64)
$x10 = COPY %4(s64)
PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
index ade3d987244e0b..c4d9e84b279ca7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
@@ -250,84 +250,6 @@ body: |
$x10 = COPY %2(s64)
...
---
-name: sh1add_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x10, $x11
-
- ; CHECK-LABEL: name: sh1add_s32
- ; CHECK: liveins: $x10, $x11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
- ; CHECK-NEXT: [[SH1ADD:%[0-9]+]]:gpr = SH1ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $x10 = COPY [[SH1ADD]]
- %0:gprb(s64) = COPY $x10
- %1:gprb(s64) = COPY $x11
- %2:gprb(s32) = G_TRUNC %0
- %3:gprb(s32) = G_TRUNC %1
- %4:gprb(s32) = G_CONSTANT i32 1
- %5:gprb(s32) = G_SHL %2, %4
- %6:gprb(s32) = G_ADD %5, %3
- %7:gprb(s64) = G_ANYEXT %6
- $x10 = COPY %7(s64)
-...
----
-name: sh2add_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x10, $x11
-
- ; CHECK-LABEL: name: sh2add_s32
- ; CHECK: liveins: $x10, $x11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
- ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $x10 = COPY [[SH2ADD]]
- %0:gprb(s64) = COPY $x10
- %1:gprb(s64) = COPY $x11
- %2:gprb(s32) = G_TRUNC %0
- %3:gprb(s32) = G_TRUNC %1
- %4:gprb(s32) = G_CONSTANT i32 2
- %5:gprb(s32) = G_SHL %2, %4
- %6:gprb(s32) = G_ADD %5, %3
- %7:gprb(s64) = G_ANYEXT %6
- $x10 = COPY %7(s64)
-...
----
-name: sh3add_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x10, $x11
-
- ; CHECK-LABEL: name: sh3add_s32
- ; CHECK: liveins: $x10, $x11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
- ; CHECK-NEXT: [[SH3ADD:%[0-9]+]]:gpr = SH3ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $x10 = COPY [[SH3ADD]]
- %0:gprb(s64) = COPY $x10
- %1:gprb(s64) = COPY $x11
- %2:gprb(s32) = G_TRUNC %0
- %3:gprb(s32) = G_TRUNC %1
- %4:gprb(s32) = G_CONSTANT i32 3
- %5:gprb(s32) = G_SHL %2, %4
- %6:gprb(s32) = G_ADD %5, %3
- %7:gprb(s64) = G_ANYEXT %6
- $x10 = COPY %7(s64)
-...
----
name: adduw
legalized: true
regBankSelected: true
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
index 115594c4b0b46b..546c15f768712a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
@@ -12,18 +12,20 @@ body: |
; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
+ ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C2]](s64)
+ ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C2]](s64)
+ ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64)
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
- ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C1]](s32)
- ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
- ; RV64I-NEXT: [[A...
[truncated]
|
|
@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesUnless the shift amount is constant. In that case we zero extend the shift amount and promote the other input the same way widenScalar would. I'm not using widenScalar because that requires a separate call for each operand so it was easier to do both operands at once. Patch is 203.34 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/115559.diff 27 Files Affected:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 91353772e201ef..c9ac45ac3519e7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -159,12 +159,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.lower();
getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
- .legalFor({{s32, s32}, {sXLen, sXLen}})
+ .legalFor({{sXLen, sXLen}})
+ .customFor(ST.is64Bit(), {{s32, s32}})
.widenScalarToNextPow2(0)
- .clampScalar(1, s32, sXLen)
- .clampScalar(0, s32, sXLen)
- .minScalarSameAs(1, 0)
- .maxScalarSameAs(1, 0);
+ .clampScalar(1, sXLen, sXLen)
+ .clampScalar(0, sXLen, sXLen);
auto &ExtActions =
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
@@ -1171,6 +1170,12 @@ static unsigned getRISCVWOpcode(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unexpected opcode");
+ case TargetOpcode::G_ASHR:
+ return RISCV::G_SRAW;
+ case TargetOpcode::G_LSHR:
+ return RISCV::G_SRLW;
+ case TargetOpcode::G_SHL:
+ return RISCV::G_SLLW;
case TargetOpcode::G_SDIV:
return RISCV::G_DIVW;
case TargetOpcode::G_UDIV:
@@ -1228,6 +1233,36 @@ bool RISCVLegalizerInfo::legalizeCustom(
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
LegalizerHelper::Legalized;
}
+ case TargetOpcode::G_ASHR:
+ case TargetOpcode::G_LSHR:
+ case TargetOpcode::G_SHL: {
+ Register AmtReg = MI.getOperand(2).getReg();
+ auto VRegAndVal = getIConstantVRegValWithLookThrough(AmtReg, MRI);
+ if (VRegAndVal) {
+ // We don't need a custom node for shift by constant. Just widen the
+ // source and the shift amount.
+ unsigned ExtOpc = TargetOpcode::G_ANYEXT;
+ if (MI.getOpcode() == TargetOpcode::G_ASHR)
+ ExtOpc = TargetOpcode::G_SEXT;
+ else if (MI.getOpcode() == TargetOpcode::G_LSHR)
+ ExtOpc = TargetOpcode::G_ZEXT;
+
+ Helper.Observer.changingInstr(MI);
+ Helper.widenScalarSrc(MI, sXLen, 1, ExtOpc);
+ Helper.widenScalarSrc(MI, sXLen, 2, TargetOpcode::G_ZEXT);
+ Helper.widenScalarDst(MI, sXLen);
+ Helper.Observer.changedInstr(MI);
+ return true;
+ }
+
+ Helper.Observer.changingInstr(MI);
+ Helper.widenScalarSrc(MI, sXLen, 1, TargetOpcode::G_ANYEXT);
+ Helper.widenScalarSrc(MI, sXLen, 2, TargetOpcode::G_ANYEXT);
+ Helper.widenScalarDst(MI, sXLen);
+ MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode())));
+ Helper.Observer.changedInstr(MI);
+ return true;
+ }
case TargetOpcode::G_SDIV:
case TargetOpcode::G_UDIV:
case TargetOpcode::G_UREM:
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index c0af1d60cb6015..08703411f126ac 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -169,6 +169,15 @@ def : LdPat<load, LD, PtrVT>;
def : StPat<store, SD, GPR, PtrVT>;
}
+let Predicates = [IsRV64] in {
+// FIXME: tblgen can't import sext_inreg patterns.
+def : Pat<(sra (sexti32 (i64 GPR:$rs1)), uimm5:$shamt),
+ (SRAIW GPR:$rs1, uimm5:$shamt)>;
+// FIXME: Temporary until i32->i64 zext is no longer legal.
+def : Pat <(srl (zext GPR:$rs1), uimm5:$shamt),
+ (SRLIW GPR:$rs1, uimm5:$shamt)>;
+}
+
//===----------------------------------------------------------------------===//
// RV64 i32 patterns not used by SelectionDAG
//===----------------------------------------------------------------------===//
@@ -201,9 +210,6 @@ def : PatGprGpr<sub, SUBW, i32, i32>;
def : PatGprGpr<and, AND, i32, i32>;
def : PatGprGpr<or, OR, i32, i32>;
def : PatGprGpr<xor, XOR, i32, i32>;
-def : PatGprGpr<shl, SLLW, i32, i32>;
-def : PatGprGpr<srl, SRLW, i32, i32>;
-def : PatGprGpr<sra, SRAW, i32, i32>;
def : Pat<(i32 (add GPR:$rs1, simm12i32:$imm)),
(ADDIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
@@ -214,13 +220,6 @@ def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
(XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
-def : Pat<(i32 (shl GPR:$rs1, uimm5i32:$imm)),
- (SLLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
-def : Pat<(i32 (srl GPR:$rs1, uimm5i32:$imm)),
- (SRLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
-def : Pat<(i32 (sra GPR:$rs1, uimm5i32:$imm)),
- (SRAIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
-
def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
(SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
(i64 (XLenSubTrailingOnes $mask)))>;
@@ -270,10 +269,4 @@ def : Pat<(shl (i64 (zext i32:$rs1)), uimm5:$shamt),
def : Pat<(i64 (add_like_non_imm12 (zext GPR:$rs1), GPR:$rs2)),
(ADD_UW GPR:$rs1, GPR:$rs2)>;
def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
-
-foreach i = {1,2,3} in {
- defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
- def : Pat<(i32 (add_like_non_imm12 (shl GPR:$rs1, (i32 i)), GPR:$rs2)),
- (shxadd GPR:$rs1, GPR:$rs2)>;
-}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
index bf2f8663cfa156..ac5f4f0ca6cc5b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td
@@ -17,6 +17,30 @@ class RISCVGenericInstruction : GenericInstruction {
let Namespace = "RISCV";
}
+// Pseudo equivalent to a RISCVISD::SRAW.
+def G_SRAW : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_SRAW, riscv_sraw>;
+
+// Pseudo equivalent to a RISCVISD::SRLW.
+def G_SRLW : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_SRLW, riscv_srlw>;
+
+// Pseudo equivalent to a RISCVISD::SLLW.
+def G_SLLW : RISCVGenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = false;
+}
+def : GINodeEquiv<G_SLLW, riscv_sllw>;
+
// Pseudo equivalent to a RISCVISD::DIVW.
def G_DIVW : RISCVGenericInstruction {
let OutOperandList = (outs type0:$dst);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
index 14ff9e01ab3bc2..30560693e8b9fd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
@@ -168,7 +168,7 @@ define i32 @slli_i32(i32 %a) {
;
; RV64IM-LABEL: slli_i32:
; RV64IM: # %bb.0: # %entry
-; RV64IM-NEXT: slliw a0, a0, 11
+; RV64IM-NEXT: slli a0, a0, 11
; RV64IM-NEXT: ret
entry:
%0 = shl i32 %a, 11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
index 5c42fefb95b39f..4c65ee94651029 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
@@ -17,7 +17,7 @@ define i2 @bitreverse_i2(i2 %x) {
; RV64-NEXT: slli a1, a0, 1
; RV64-NEXT: andi a1, a1, 2
; RV64-NEXT: andi a0, a0, 3
-; RV64-NEXT: srliw a0, a0, 1
+; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i2 @llvm.bitreverse.i2(i2 %x)
@@ -43,7 +43,7 @@ define i3 @bitreverse_i3(i3 %x) {
; RV64-NEXT: andi a0, a0, 7
; RV64-NEXT: andi a2, a0, 2
; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: srliw a0, a0, 2
+; RV64-NEXT: srli a0, a0, 2
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i3 @llvm.bitreverse.i3(i3 %x)
@@ -74,10 +74,10 @@ define i4 @bitreverse_i4(i4 %x) {
; RV64-NEXT: andi a2, a2, 4
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: andi a0, a0, 15
-; RV64-NEXT: srliw a2, a0, 1
+; RV64-NEXT: srli a2, a0, 1
; RV64-NEXT: andi a2, a2, 2
; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: srliw a0, a0, 3
+; RV64-NEXT: srli a0, a0, 3
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i4 @llvm.bitreverse.i4(i4 %x)
@@ -121,13 +121,13 @@ define i7 @bitreverse_i7(i7 %x) {
; RV64-NEXT: andi a3, a0, 8
; RV64-NEXT: or a2, a2, a3
; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: srliw a2, a0, 2
+; RV64-NEXT: srli a2, a0, 2
; RV64-NEXT: andi a2, a2, 4
-; RV64-NEXT: srliw a3, a0, 4
+; RV64-NEXT: srli a3, a0, 4
; RV64-NEXT: andi a3, a3, 2
; RV64-NEXT: or a2, a2, a3
; RV64-NEXT: or a1, a1, a2
-; RV64-NEXT: srliw a0, a0, 6
+; RV64-NEXT: srli a0, a0, 6
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i7 @llvm.bitreverse.i7(i7 %x)
@@ -171,36 +171,36 @@ define i24 @bitreverse_i24(i24 %x) {
;
; RV64-LABEL: bitreverse_i24:
; RV64: # %bb.0:
-; RV64-NEXT: slli a1, a0, 16
-; RV64-NEXT: lui a2, 4096
-; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: srliw a0, a0, 16
-; RV64-NEXT: or a0, a0, a1
-; RV64-NEXT: lui a1, 1048335
-; RV64-NEXT: addi a1, a1, 240
-; RV64-NEXT: and a3, a1, a2
+; RV64-NEXT: lui a1, 4096
+; RV64-NEXT: addiw a1, a1, -1
+; RV64-NEXT: slli a2, a0, 16
+; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: srli a0, a0, 16
+; RV64-NEXT: or a0, a0, a2
+; RV64-NEXT: lui a2, 1048335
+; RV64-NEXT: addiw a2, a2, 240
+; RV64-NEXT: and a3, a2, a1
; RV64-NEXT: and a3, a0, a3
-; RV64-NEXT: srliw a3, a3, 4
+; RV64-NEXT: srli a3, a3, 4
; RV64-NEXT: slli a0, a0, 4
-; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: or a0, a3, a0
-; RV64-NEXT: lui a1, 1047757
-; RV64-NEXT: addi a1, a1, -820
-; RV64-NEXT: and a3, a1, a2
+; RV64-NEXT: lui a2, 1047757
+; RV64-NEXT: addiw a2, a2, -820
+; RV64-NEXT: and a3, a2, a1
; RV64-NEXT: and a3, a0, a3
-; RV64-NEXT: srliw a3, a3, 2
+; RV64-NEXT: srli a3, a3, 2
; RV64-NEXT: slli a0, a0, 2
-; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: or a0, a3, a0
-; RV64-NEXT: lui a1, 1047211
-; RV64-NEXT: addiw a1, a1, -1366
-; RV64-NEXT: and a2, a1, a2
-; RV64-NEXT: and a2, a0, a2
-; RV64-NEXT: srliw a2, a2, 1
-; RV64-NEXT: slliw a0, a0, 1
-; RV64-NEXT: and a0, a0, a1
-; RV64-NEXT: or a0, a2, a0
+; RV64-NEXT: lui a2, 1047211
+; RV64-NEXT: addiw a2, a2, -1366
+; RV64-NEXT: and a1, a2, a1
+; RV64-NEXT: and a1, a0, a1
+; RV64-NEXT: srli a1, a1, 1
+; RV64-NEXT: slli a0, a0, 1
+; RV64-NEXT: and a0, a0, a2
+; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i24 @llvm.bitreverse.i24(i24 %x)
ret i24 %rev
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
index 6bdc7ce0249197..9093e625d8e429 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
@@ -42,10 +42,18 @@ define i32 @mul_to_shift(i32 %x) {
; RV32-NEXT: slli a0, a0, 2
; RV32-NEXT: ret
;
-; RV64-LABEL: mul_to_shift:
-; RV64: # %bb.0:
-; RV64-NEXT: slliw a0, a0, 2
-; RV64-NEXT: ret
+; RV64-O0-LABEL: mul_to_shift:
+; RV64-O0: # %bb.0:
+; RV64-O0-NEXT: li a1, 2
+; RV64-O0-NEXT: sll a0, a0, a1
+; RV64-O0-NEXT: ret
+;
+; RV64-OPT-LABEL: mul_to_shift:
+; RV64-OPT: # %bb.0:
+; RV64-OPT-NEXT: slli a0, a0, 2
+; RV64-OPT-NEXT: ret
%a = mul i32 %x, 4
ret i32 %a
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
index 32593a74d307ef..7ba3fb055ca1eb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
@@ -32,9 +32,9 @@ define i8 @abs8(i8 %x) {
;
; RV64I-LABEL: abs8:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 24
-; RV64I-NEXT: sraiw a1, a1, 24
-; RV64I-NEXT: sraiw a1, a1, 7
+; RV64I-NEXT: slli a1, a0, 56
+; RV64I-NEXT: srai a1, a1, 56
+; RV64I-NEXT: srai a1, a1, 7
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
@@ -68,9 +68,9 @@ define i16 @abs16(i16 %x) {
;
; RV64I-LABEL: abs16:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: sraiw a1, a1, 16
-; RV64I-NEXT: sraiw a1, a1, 15
+; RV64I-NEXT: slli a1, a0, 48
+; RV64I-NEXT: srai a1, a1, 48
+; RV64I-NEXT: srai a1, a1, 15
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
index 527036d8b750fc..f896ee934fc8c0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
@@ -219,12 +219,9 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SLLW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s64) = COPY $x11
- %3:gprb(s32) = G_TRUNC %2(s64)
- %4:gprb(s32) = G_SHL %1, %3(s32)
- %5:gprb(s64) = G_ANYEXT %4(s32)
- $x10 = COPY %5(s64)
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_SLLW %0, %1
+ $x10 = COPY %2(s64)
PseudoRET implicit $x10
...
@@ -241,15 +238,13 @@ body: |
; RV64I: liveins: $x10
; RV64I-NEXT: {{ $}}
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; RV64I-NEXT: [[SLLIW:%[0-9]+]]:gpr = SLLIW [[COPY]], 31
- ; RV64I-NEXT: $x10 = COPY [[SLLIW]]
+ ; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31
+ ; RV64I-NEXT: $x10 = COPY [[SLLI]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s32) = G_CONSTANT i32 31
- %3:gprb(s32) = G_SHL %1, %2
- %4:gprb(s64) = G_ANYEXT %3(s32)
- $x10 = COPY %4(s64)
+ %1:gprb(s64) = G_CONSTANT i64 31
+ %2:gprb(s64) = G_SHL %0, %1
+ $x10 = COPY %2(s64)
PseudoRET implicit $x10
...
@@ -271,12 +266,9 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SRAW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s64) = COPY $x11
- %3:gprb(s32) = G_TRUNC %2(s64)
- %4:gprb(s32) = G_ASHR %1, %3(s32)
- %5:gprb(s64) = G_ANYEXT %4(s32)
- $x10 = COPY %5(s64)
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_SRAW %0, %1
+ $x10 = COPY %2(s64)
PseudoRET implicit $x10
...
@@ -297,11 +289,10 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SRAIW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s32) = G_CONSTANT i32 31
- %3:gprb(s32) = G_ASHR %1, %2
- %4:gprb(s64) = G_ANYEXT %3(s32)
- $x10 = COPY %4(s64)
+ %1:gprb(s64) = G_CONSTANT i64 31
+ %2:gprb(s64) = G_SEXT_INREG %0, 32
+ %3:gprb(s64) = G_ASHR %2, %1(s64)
+ $x10 = COPY %3(s64)
PseudoRET implicit $x10
...
@@ -323,12 +314,9 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SRLW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s64) = COPY $x11
- %3:gprb(s32) = G_TRUNC %2(s64)
- %4:gprb(s32) = G_LSHR %1, %3(s32)
- %5:gprb(s64) = G_ANYEXT %4(s32)
- $x10 = COPY %5(s64)
+ %1:gprb(s64) = COPY $x11
+ %2:gprb(s64) = G_SRLW %0, %1
+ $x10 = COPY %2(s64)
PseudoRET implicit $x10
...
@@ -349,10 +337,10 @@ body: |
; RV64I-NEXT: $x10 = COPY [[SRLIW]]
; RV64I-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
- %1:gprb(s32) = G_TRUNC %0(s64)
- %2:gprb(s32) = G_CONSTANT i32 31
- %3:gprb(s32) = G_LSHR %1, %2
- %4:gprb(s64) = G_ANYEXT %3(s32)
+ %1:gprb(s64) = G_CONSTANT i64 31
+ %2:gprb(s64) = G_CONSTANT i64 4294967295
+ %3:gprb(s64) = G_AND %0, %2
+ %4:gprb(s64) = G_LSHR %3, %1(s64)
$x10 = COPY %4(s64)
PseudoRET implicit $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
index ade3d987244e0b..c4d9e84b279ca7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
@@ -250,84 +250,6 @@ body: |
$x10 = COPY %2(s64)
...
---
-name: sh1add_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x10, $x11
-
- ; CHECK-LABEL: name: sh1add_s32
- ; CHECK: liveins: $x10, $x11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
- ; CHECK-NEXT: [[SH1ADD:%[0-9]+]]:gpr = SH1ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $x10 = COPY [[SH1ADD]]
- %0:gprb(s64) = COPY $x10
- %1:gprb(s64) = COPY $x11
- %2:gprb(s32) = G_TRUNC %0
- %3:gprb(s32) = G_TRUNC %1
- %4:gprb(s32) = G_CONSTANT i32 1
- %5:gprb(s32) = G_SHL %2, %4
- %6:gprb(s32) = G_ADD %5, %3
- %7:gprb(s64) = G_ANYEXT %6
- $x10 = COPY %7(s64)
-...
----
-name: sh2add_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x10, $x11
-
- ; CHECK-LABEL: name: sh2add_s32
- ; CHECK: liveins: $x10, $x11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
- ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $x10 = COPY [[SH2ADD]]
- %0:gprb(s64) = COPY $x10
- %1:gprb(s64) = COPY $x11
- %2:gprb(s32) = G_TRUNC %0
- %3:gprb(s32) = G_TRUNC %1
- %4:gprb(s32) = G_CONSTANT i32 2
- %5:gprb(s32) = G_SHL %2, %4
- %6:gprb(s32) = G_ADD %5, %3
- %7:gprb(s64) = G_ANYEXT %6
- $x10 = COPY %7(s64)
-...
----
-name: sh3add_s32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x10, $x11
-
- ; CHECK-LABEL: name: sh3add_s32
- ; CHECK: liveins: $x10, $x11
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
- ; CHECK-NEXT: [[SH3ADD:%[0-9]+]]:gpr = SH3ADD [[COPY]], [[COPY1]]
- ; CHECK-NEXT: $x10 = COPY [[SH3ADD]]
- %0:gprb(s64) = COPY $x10
- %1:gprb(s64) = COPY $x11
- %2:gprb(s32) = G_TRUNC %0
- %3:gprb(s32) = G_TRUNC %1
- %4:gprb(s32) = G_CONSTANT i32 3
- %5:gprb(s32) = G_SHL %2, %4
- %6:gprb(s32) = G_ADD %5, %3
- %7:gprb(s64) = G_ANYEXT %6
- $x10 = COPY %7(s64)
-...
----
name: adduw
legalized: true
regBankSelected: true
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
index 115594c4b0b46b..546c15f768712a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
@@ -12,18 +12,20 @@ body: |
; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
+ ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
+ ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C2]](s64)
+ ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C2]](s64)
+ ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64)
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
- ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C1]](s32)
- ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
- ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
- ; RV64I-NEXT: [[A...
[truncated]
|
mshockwave
approved these changes
Nov 12, 2024
Comment on lines
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| auto VRegAndVal = getIConstantVRegValWithLookThrough(AmtReg, MRI); | ||
| if (VRegAndVal) { |
There was a problem hiding this comment.
Suggested change
| auto VRegAndVal = getIConstantVRegValWithLookThrough(AmtReg, MRI); | |
| if (VRegAndVal) { | |
| if (getIConstantVRegValWithLookThrough(AmtReg, MRI)) { |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/179/builds/10065 Here is the relevant piece of the build log for the reference |
Groverkss
pushed a commit
to iree-org/llvm-project
that referenced
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Nov 15, 2024
Unless the shift amount is constant. In that case we zero extend the shift amount and promote the other input the same way widenScalar would. I'm not using widenScalar because that requires a separate call for each operand so it was easier to do both operands at once.
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Unless the shift amount is constant. In that case we zero extend the shift amount and promote the other input the same way widenScalar would. I'm not using widenScalar because that requires a separate call for each operand so it was easier to do both operands at once.