[AMDGPU] Reorder GCNPassConfig::addOptimizedRegAlloc. NFC. #115873
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This just makes it so that the added passes are mentioned in this function in the same order that they will appear in the final pass pipeline.
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@llvm/pr-subscribers-backend-amdgpu Author: Jay Foad (jayfoad) ChangesThis just makes it so that the added passes are mentioned in this Full diff: https://github.com/llvm/llvm-project/pull/115873.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 786baa6820e860..06ed92e22e6539 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1415,23 +1415,8 @@ void GCNPassConfig::addFastRegAlloc() {
}
void GCNPassConfig::addOptimizedRegAlloc() {
- // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
- // instructions that cause scheduling barriers.
- insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
-
- if (OptExecMaskPreRA)
- insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
-
- if (EnableRewritePartialRegUses)
- insertPass(&RenameIndependentSubregsID, &GCNRewritePartialRegUsesID);
-
- if (isPassEnabled(EnablePreRAOptimizations))
- insertPass(&RenameIndependentSubregsID, &GCNPreRAOptimizationsID);
-
- // This is not an essential optimization and it has a noticeable impact on
- // compilation time, so we only enable it from O2.
- if (TM->getOptLevel() > CodeGenOptLevel::Less)
- insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
+ if (EnableDCEInRA)
+ insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
// FIXME: when an instruction has a Killed operand, and the instruction is
// inside a bundle, seems only the BUNDLE instruction appears as the Kills of
@@ -1439,13 +1424,29 @@ void GCNPassConfig::addOptimizedRegAlloc() {
// we should fix it and enable the verifier.
if (OptVGPRLiveRange)
insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID);
+
// This must be run immediately after phi elimination and before
// TwoAddressInstructions, otherwise the processing of the tied operand of
// SI_ELSE will introduce a copy of the tied operand source after the else.
insertPass(&PHIEliminationID, &SILowerControlFlowID);
- if (EnableDCEInRA)
- insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
+ if (EnableRewritePartialRegUses)
+ insertPass(&RenameIndependentSubregsID, &GCNRewritePartialRegUsesID);
+
+ if (isPassEnabled(EnablePreRAOptimizations))
+ insertPass(&RenameIndependentSubregsID, &GCNPreRAOptimizationsID);
+
+ // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
+ // instructions that cause scheduling barriers.
+ insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
+
+ if (OptExecMaskPreRA)
+ insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
+
+ // This is not an essential optimization and it has a noticeable impact on
+ // compilation time, so we only enable it from O2.
+ if (TM->getOptLevel() > CodeGenOptLevel::Less)
+ insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
TargetPassConfig::addOptimizedRegAlloc();
}
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arsenm
approved these changes
Nov 12, 2024
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/18/builds/6888 Here is the relevant piece of the build log for the reference |
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This just makes it so that the added passes are mentioned in this
function in the same order that they will appear in the final pass
pipeline.