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[RISCV][MachineVerifier] Use RegUnit for register liveness checking #115980

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Merged
merged 6 commits into from
Nov 25, 2024
Merged

[RISCV][MachineVerifier] Use RegUnit for register liveness checking #115980

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ad9a2ad
[RISCV][MachineVerifier] Treat register as live when all its units be…
BeMg Nov 11, 2024
152de89
Move testcase into test/MachineVerifier/RISCV
BeMg Nov 14, 2024
e30ab9b
Reduce the testcase
BeMg Nov 14, 2024
20c4b53
Remove the redundant checking
BeMg Nov 14, 2024
2a6399a
Add comment
BeMg Nov 18, 2024
3f8f57f
Drop subreg check liveness
BeMg Nov 18, 2024
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6 changes: 5 additions & 1 deletion llvm/lib/CodeGen/MachineVerifier.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3033,7 +3033,11 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
if (!MOP.getReg().isPhysical())
continue;

if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
if (MOP.getReg() != Reg &&
all_of(TRI->regunits(Reg), [&](const MCRegUnit RegUnit) {
return llvm::is_contained(TRI->regunits(MOP.getReg()),
RegUnit);
}))
Bad = false;
}
}
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26 changes: 26 additions & 0 deletions llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
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@@ -0,0 +1,26 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=none %s -o - | FileCheck %s

# During the MachineVerifier, it assumes that used registers have been defined
# In this test case, while $v12_v13_v14_v15_v16 covers $v14_v15,
# $v14_v15 is not a sub-register of $v14m2 even though they share the same register.
# This corner case can be resolved by checking the register using RegUnit.

...
---
name: func
tracksRegLiveness: true
tracksDebugUserValues: true
body: |
bb.0:
liveins: $v0, $v8, $v9, $v10, $v11

; CHECK-LABEL: name: func
; CHECK: liveins: $v0, $v8, $v9, $v10, $v11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16
renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
$v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16

...
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