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[clang-format] Stop crashing on slightly off Verilog module headers #116000

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Merged
merged 1 commit into from
Nov 20, 2024
Merged

[clang-format] Stop crashing on slightly off Verilog module headers #116000

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4 changes: 2 additions & 2 deletions clang/lib/Format/TokenAnnotator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1554,7 +1554,7 @@ class AnnotatingParser {
};

if (IsInstancePort())
Tok->setFinalizedType(TT_VerilogInstancePortLParen);
Tok->setType(TT_VerilogInstancePortLParen);
}

if (!parseParens())
Expand Down Expand Up @@ -1730,7 +1730,7 @@ class AnnotatingParser {
Tok->setType(TT_InheritanceComma);
break;
case Context::VerilogInstancePortList:
Tok->setFinalizedType(TT_VerilogInstancePortComma);
Tok->setType(TT_VerilogInstancePortComma);
break;
default:
if (Style.isVerilog() && Contexts.size() == 1 &&
Expand Down
3 changes: 2 additions & 1 deletion clang/lib/Format/UnwrappedLineParser.cpp
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Expand Up @@ -4441,7 +4441,8 @@ unsigned UnwrappedLineParser::parseVerilogHierarchyHeader() {
Prev->setFinalizedType(TT_VerilogDimensionedTypeName);
parseSquare();
} else if (Keywords.isVerilogIdentifier(*FormatTok) ||
FormatTok->isOneOf(Keywords.kw_automatic, tok::kw_static)) {
FormatTok->isOneOf(tok::hash, tok::hashhash, tok::coloncolon,
Keywords.kw_automatic, tok::kw_static)) {
nextToken();
} else {
break;
Expand Down
12 changes: 12 additions & 0 deletions clang/unittests/Format/FormatTestVerilog.cpp
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Expand Up @@ -702,6 +702,18 @@ TEST_F(FormatTestVerilog, Hierarchy) {
" generate\n"
" endgenerate\n"
"endfunction : x");
// Type names with '::' should be recognized.
verifyFormat("function automatic x::x x\n"
" (input x);\n"
"endfunction : x");
// Names having to do macros should be recognized.
verifyFormat("function automatic x::x x``x\n"
" (input x);\n"
"endfunction : x");
verifyFormat("function automatic x::x `x\n"
" (input x);\n"
"endfunction : x");
verifyNoCrash("x x(x x, x x);");
}

TEST_F(FormatTestVerilog, Identifiers) {
Expand Down
14 changes: 14 additions & 0 deletions clang/unittests/Format/TokenAnnotatorTest.cpp
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Expand Up @@ -2598,6 +2598,20 @@ TEST_F(TokenAnnotatorTest, UnderstandsVerilogOperators) {
Tokens = Annotate("x = '{\"\"};");
ASSERT_EQ(Tokens.size(), 8u) << Tokens;
EXPECT_TOKEN(Tokens[4], tok::string_literal, TT_Unknown);

// Module headers.
Tokens = Annotate("module x();\nendmodule");
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This (and other testcases below) should be broken up into two lines:

  Tokens = Annotate("module x();\n"
                    "endmodule");

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Fixed in aa2d084.

ASSERT_EQ(Tokens.size(), 7u) << Tokens;
EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_VerilogMultiLineListLParen);
Tokens = Annotate("function automatic `x x();\nendmodule");
ASSERT_EQ(Tokens.size(), 10u) << Tokens;
EXPECT_TOKEN(Tokens[5], tok::l_paren, TT_VerilogMultiLineListLParen);
Tokens = Annotate("function automatic x``x x();\nendmodule");
ASSERT_EQ(Tokens.size(), 11u) << Tokens;
EXPECT_TOKEN(Tokens[6], tok::l_paren, TT_VerilogMultiLineListLParen);
Tokens = Annotate("function automatic x::x x();\nendmodule");
ASSERT_EQ(Tokens.size(), 11u) << Tokens;
EXPECT_TOKEN(Tokens[6], tok::l_paren, TT_VerilogMultiLineListLParen);
}

TEST_F(TokenAnnotatorTest, UnderstandTableGenTokens) {
Expand Down
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