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[AMDGPU][True16][MC] Implement V_CVT_PK_F32_FP8/BF8 #116106

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Merged
merged 1 commit into from
Nov 14, 2024
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[AMDGPU][True16][MC] Implement V_CVT_PK_F32_FP8/BF8 #116106

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6 changes: 4 additions & 2 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -588,8 +588,10 @@ bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc) {
Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 ||
Opc == AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12;
Opc == AMDGPU::V_CVT_PK_F32_BF8_fake16_e64_gfx12 ||
Opc == AMDGPU::V_CVT_PK_F32_FP8_fake16_e64_gfx12 ||
Opc == AMDGPU::V_CVT_PK_F32_BF8_t16_e64_gfx12 ||
Opc == AMDGPU::V_CVT_PK_F32_FP8_t16_e64_gfx12;
}

bool isGenericAtomic(unsigned Opc) {
Expand Down
51 changes: 29 additions & 22 deletions llvm/lib/Target/AMDGPU/VOP1Instructions.td
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Expand Up @@ -634,17 +634,16 @@ let SubtargetPredicate = HasFP8ConversionInsts, OtherPredicates = [HasSDWA] in {
}
}


// Similar to VOPProfile_Base_CVT_F32_F8, but for VOP3 instructions.
def VOPProfile_Base_CVT_PK_F32_F8_OpSel : VOPProfile<[v2f32, i32, untyped, untyped]> {
let HasOpSel = 1;
let HasClamp = 0;
let HasOMod = 0;
let HasExtDPP = 0;
let HasExtVOP3DPP = 0;
let AsmVOP3Base = getAsmVOP3Base<NumSrcArgs, HasDst, HasClamp,
HasOpSel, HasOMod, IsVOP3P, 0 /*HasModifiers*/, 0/*Src0HasMods*/, 0/*Src1HasMods*/,
0/*Src2HasMods*/, DstVT>.ret;
let HasClamp = 0, HasOMod = 0, HasExtDPP = 0, HasExtVOP3DPP = 0,
HasOpSel = 1 in {
// Input modifiers are not supported
// NB: fake16 VOP1 does not support op_sel.
def VOPProfile_Base_CVT_PK_F32_F8_fake16 : VOPProfile_Fake16<VOPProfile<[v2f32, f16, untyped, untyped]>> {
let Src0Mod = IntT16InputMods<1/*IsFake16*/>;
}
def VOPProfile_Base_CVT_PK_F32_F8_t16 : VOPProfile_True16<VOPProfile<[v2f32, f16, untyped, untyped]>> {
let Src0Mod = IntT16InputMods<0/*IsFake16*/>;
}
}

class VOPProfile_Base_CVT_F_F8_ByteSel<ValueType DstVT> : VOPProfile<[DstVT, i32, untyped, untyped]> {
Expand Down Expand Up @@ -673,8 +672,15 @@ let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts],
mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in {
defm V_CVT_F32_FP8_OP_SEL : VOP1Inst<"v_cvt_f32_fp8_op_sel", VOPProfile_Base_CVT_F_F8_ByteSel<f32>>;
defm V_CVT_F32_BF8_OP_SEL : VOP1Inst<"v_cvt_f32_bf8_op_sel", VOPProfile_Base_CVT_F_F8_ByteSel<f32>>;
defm V_CVT_PK_F32_FP8_OP_SEL : VOP1Inst<"v_cvt_pk_f32_fp8_op_sel", VOPProfile_Base_CVT_PK_F32_F8_OpSel>;
defm V_CVT_PK_F32_BF8_OP_SEL : VOP1Inst<"v_cvt_pk_f32_bf8_op_sel", VOPProfile_Base_CVT_PK_F32_F8_OpSel>;

let True16Predicate = UseFakeTrue16Insts in {
defm V_CVT_PK_F32_FP8_fake16 : VOP1Inst<"v_cvt_pk_f32_fp8_fake16", VOPProfile_Base_CVT_PK_F32_F8_fake16>;
defm V_CVT_PK_F32_BF8_fake16 : VOP1Inst<"v_cvt_pk_f32_bf8_fake16", VOPProfile_Base_CVT_PK_F32_F8_fake16>;
}
let True16Predicate = UseRealTrue16Insts in {
defm V_CVT_PK_F32_FP8_t16 : VOP1Inst<"v_cvt_pk_f32_fp8_t16", VOPProfile_Base_CVT_PK_F32_F8_t16>;
defm V_CVT_PK_F32_BF8_t16 : VOP1Inst<"v_cvt_pk_f32_bf8_t16", VOPProfile_Base_CVT_PK_F32_F8_t16>;
}
}

class Cvt_F_F8_Pat_ByteSel<SDPatternOperator node, VOP3_Pseudo inst> : GCNPat<
Expand All @@ -698,9 +704,9 @@ class Cvt_PK_F32_F8_Pat_OpSel<SDPatternOperator node, int index,
let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts] in {
foreach Index = [0, -1] in {
def : Cvt_PK_F32_F8_Pat_OpSel<int_amdgcn_cvt_pk_f32_fp8, Index,
V_CVT_PK_F32_FP8_e32, V_CVT_PK_F32_FP8_OP_SEL_e64>;
V_CVT_PK_F32_FP8_fake16_e32, V_CVT_PK_F32_FP8_fake16_e64>;
def : Cvt_PK_F32_F8_Pat_OpSel<int_amdgcn_cvt_pk_f32_bf8, Index,
V_CVT_PK_F32_BF8_e32, V_CVT_PK_F32_BF8_OP_SEL_e64>;
V_CVT_PK_F32_BF8_fake16_e32, V_CVT_PK_F32_BF8_fake16_e64>;
}
}

Expand Down Expand Up @@ -954,13 +960,14 @@ multiclass VOP1_Real_NO_DPP_OP_SEL_with_name<GFXGen Gen, bits<9> op,
defm V_CVT_F32_FP8 : VOP1_Real_FULL_with_name<GFX12Gen, 0x06c, "V_CVT_F32_FP8_OP_SEL", "v_cvt_f32_fp8">;
defm V_CVT_F32_BF8 : VOP1_Real_FULL_with_name<GFX12Gen, 0x06d, "V_CVT_F32_BF8_OP_SEL", "v_cvt_f32_bf8">;

// Define VOP1 instructions using the pseudo instruction with its old profile and
// VOP3 using the OpSel profile for the pseudo instruction.
defm V_CVT_PK_F32_FP8 : VOP1_Real_e32_with_name<GFX12Gen, 0x06e, "V_CVT_PK_F32_FP8", "v_cvt_pk_f32_fp8">;
defm V_CVT_PK_F32_FP8 : VOP3_Real_with_name<GFX12Gen, 0x1ee, "V_CVT_PK_F32_FP8_OP_SEL", "v_cvt_pk_f32_fp8">;

defm V_CVT_PK_F32_BF8 : VOP1_Real_e32_with_name<GFX12Gen, 0x06f, "V_CVT_PK_F32_BF8", "v_cvt_pk_f32_bf8">;
defm V_CVT_PK_F32_BF8 : VOP3_Real_with_name<GFX12Gen, 0x1ef, "V_CVT_PK_F32_BF8_OP_SEL", "v_cvt_pk_f32_bf8">;
defm V_CVT_PK_F32_FP8_fake16 : VOP1_Real_e32_with_name<GFX12Gen, 0x06e, "V_CVT_PK_F32_FP8_fake16", "v_cvt_pk_f32_fp8">;
defm V_CVT_PK_F32_FP8_t16 : VOP1_Real_e32_with_name<GFX12Gen, 0x06e, "V_CVT_PK_F32_FP8_t16", "v_cvt_pk_f32_fp8">;
defm V_CVT_PK_F32_FP8_fake16 : VOP3_Real_with_name<GFX12Gen, 0x1ee, "V_CVT_PK_F32_FP8_fake16", "v_cvt_pk_f32_fp8">;
defm V_CVT_PK_F32_FP8_t16 : VOP3_Real_with_name<GFX12Gen, 0x1ee, "V_CVT_PK_F32_FP8_t16", "v_cvt_pk_f32_fp8">;
defm V_CVT_PK_F32_BF8_fake16 : VOP1_Real_e32_with_name<GFX12Gen, 0x06f, "V_CVT_PK_F32_BF8_fake16", "v_cvt_pk_f32_bf8">;
defm V_CVT_PK_F32_BF8_t16 : VOP1_Real_e32_with_name<GFX12Gen, 0x06f, "V_CVT_PK_F32_BF8_t16", "v_cvt_pk_f32_bf8">;
defm V_CVT_PK_F32_BF8_fake16 : VOP3_Real_with_name<GFX12Gen, 0x1ef, "V_CVT_PK_F32_BF8_fake16", "v_cvt_pk_f32_bf8">;
defm V_CVT_PK_F32_BF8_t16 : VOP3_Real_with_name<GFX12Gen, 0x1ef, "V_CVT_PK_F32_BF8_t16", "v_cvt_pk_f32_bf8">;

defm V_CVT_NEAREST_I32_F32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x00c,
"V_CVT_RPI_I32_F32", "v_cvt_nearest_i32_f32">;
Expand Down
18 changes: 12 additions & 6 deletions llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
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Expand Up @@ -429,20 +429,26 @@ v_cvt_pk_f32_bf8_e32 v[2:3], 3
v_cvt_pk_f32_bf8_e32 v[3:4], 3
// GFX12: v_cvt_pk_f32_bf8_e32 v[3:4], 3 ; encoding: [0x83,0xde,0x06,0x7e]

v_cvt_pk_f32_bf8_e32 v[2:3], v3
// GFX12: v_cvt_pk_f32_bf8_e32 v[2:3], v3 ; encoding: [0x03,0xdf,0x04,0x7e]
v_cvt_pk_f32_bf8_e32 v[2:3], v3.l
// GFX12: v_cvt_pk_f32_bf8_e32 v[2:3], v3.l ; encoding: [0x03,0xdf,0x04,0x7e]

v_cvt_pk_f32_bf8_e32 v[3:4], v3
// GFX12: v_cvt_pk_f32_bf8_e32 v[3:4], v3 ; encoding: [0x03,0xdf,0x06,0x7e]
v_cvt_pk_f32_bf8_e32 v[3:4], v3.l
// GFX12: v_cvt_pk_f32_bf8_e32 v[3:4], v3.l ; encoding: [0x03,0xdf,0x06,0x7e]

v_cvt_pk_f32_bf8_e32 v[3:4], v3.h
// GFX12: v_cvt_pk_f32_bf8_e32 v[3:4], v3.h ; encoding: [0x83,0xdf,0x06,0x7e]

v_cvt_pk_f32_fp8_e32 v[2:3], s3
// GFX12: v_cvt_pk_f32_fp8_e32 v[2:3], s3 ; encoding: [0x03,0xdc,0x04,0x7e]

v_cvt_pk_f32_fp8_e32 v[2:3], 3
// GFX12: v_cvt_pk_f32_fp8_e32 v[2:3], 3 ; encoding: [0x83,0xdc,0x04,0x7e]

v_cvt_pk_f32_fp8_e32 v[2:3], v3
// GFX12: v_cvt_pk_f32_fp8_e32 v[2:3], v3 ; encoding: [0x03,0xdd,0x04,0x7e]
v_cvt_pk_f32_fp8_e32 v[2:3], v3.l
// GFX12: v_cvt_pk_f32_fp8_e32 v[2:3], v3.l ; encoding: [0x03,0xdd,0x04,0x7e]

v_cvt_pk_f32_fp8_e32 v[2:3], v3.h
// GFX12: v_cvt_pk_f32_fp8_e32 v[2:3], v3.h ; encoding: [0x83,0xdd,0x04,0x7e]

v_cvt_f16_f32 v5.l, v1
// GFX12: v_cvt_f16_f32_e32 v5.l, v1 ; encoding: [0x01,0x15,0x0a,0x7e]
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
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Expand Up @@ -486,6 +486,12 @@ v_cvt_pk_f32_bf8_e64 v[2:3], v3
v_cvt_pk_f32_bf8_e64 v[2:3], v3 op_sel:[1,0]
// GFX12: encoding: [0x02,0x08,0xef,0xd5,0x03,0x01,0x00,0x00]

v_cvt_pk_f32_bf8_e64 v[2:3], v3.h
// GFX12: encoding: [0x02,0x08,0xef,0xd5,0x03,0x01,0x00,0x00]

v_cvt_pk_f32_bf8_e64 v[2:3], v255.h
// GFX12: encoding: [0x02,0x08,0xef,0xd5,0xff,0x01,0x00,0x00]

v_cvt_pk_f32_fp8_e64 v[2:3], s3
// GFX12: encoding: [0x02,0x00,0xee,0xd5,0x03,0x00,0x00,0x00]

Expand Down Expand Up @@ -534,6 +540,12 @@ v_cvt_pk_f32_fp8_e64 v[3:4], v3
v_cvt_pk_f32_fp8_e64 v[3:4], v3 op_sel:[1,0]
// GFX12: encoding: [0x03,0x08,0xee,0xd5,0x03,0x01,0x00,0x00]

v_cvt_pk_f32_fp8_e64 v[3:4], v3.h
// GFX12: encoding: [0x03,0x08,0xee,0xd5,0x03,0x01,0x00,0x00]

v_cvt_pk_f32_fp8_e64 v[3:4], v255.h
// GFX12: encoding: [0x03,0x08,0xee,0xd5,0xff,0x01,0x00,0x00]

v_cvt_f16_f32_e64 v5.l, v1
// GFX12: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]

Expand Down
18 changes: 16 additions & 2 deletions llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
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Expand Up @@ -436,18 +436,32 @@
# GFX12: v_cvt_pk_f32_bf8_e64 v[2:3], 3 ; encoding: [0x02,0x00,0xef,0xd5,0x83,0x00,0x00,0x00]
0x02,0x00,0xef,0xd5,0x83,0x00,0x00,0x00

# GFX12: v_cvt_pk_f32_bf8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x01,0x00,0x00]
# GFX12-REAL16: v_cvt_pk_f32_bf8_e64 v[2:3], v3.l ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x01,0x00,0x00]
# GFX12-FAKE16: v_cvt_pk_f32_bf8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x01,0x00,0x00]
0x02,0x00,0xef,0xd5,0x03,0x01,0x00,0x00

# GFX12-REAL16: v_cvt_pk_f32_bf8_e64 v[2:3], v3.h op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x03,0x01,0x00,0x00]
0x02,0x08,0xef,0xd5,0x03,0x01,0x00,0x00

# GFX12-REAL16: v_cvt_pk_f32_bf8_e64 v[2:3], v255.h op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0xff,0x01,0x00,0x00]
0x02,0x08,0xef,0xd5,0xff,0x01,0x00,0x00

# GFX12: v_cvt_pk_f32_fp8_e64 v[2:3], s3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x00,0x00,0x00]
0x02,0x00,0xee,0xd5,0x03,0x00,0x00,0x00

# GFX12: v_cvt_pk_f32_fp8_e64 v[2:3], 3 ; encoding: [0x02,0x00,0xee,0xd5,0x83,0x00,0x00,0x00]
0x02,0x00,0xee,0xd5,0x83,0x00,0x00,0x00

# GFX12: v_cvt_pk_f32_fp8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x01,0x00,0x00]
# GFX12-REAL16: v_cvt_pk_f32_fp8_e64 v[2:3], v3.l ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x01,0x00,0x00]
# GFX12-FAKE16: v_cvt_pk_f32_fp8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x01,0x00,0x00]
0x02,0x00,0xee,0xd5,0x03,0x01,0x00,0x00

# GFX12-REAL16: v_cvt_pk_f32_fp8_e64 v[2:3], v3.h op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x03,0x01,0x00,0x00]
0x02,0x08,0xee,0xd5,0x03,0x01,0x00,0x00

# GFX12-REAL16: v_cvt_pk_f32_fp8_e64 v[2:3], v255.h op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0xff,0x01,0x00,0x00]
0x02,0x08,0xee,0xd5,0xff,0x01,0x00,0x00

# GFX12-REAL16: v_cvt_f16_f32_e64 v5.l, v1 ; encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]
# GFX12-FAKE16: v_cvt_f16_f32_e64 v5, v1 ; encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]
0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00
Expand Down
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