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[GISel][RISCV] Add G_SMIN/SMAX/UMIN/UMAX to GISelKnownBits::computeNumSignBits. #116321

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Merged
merged 1 commit into from
Nov 15, 2024
Merged

[GISel][RISCV] Add G_SMIN/SMAX/UMIN/UMAX to GISelKnownBits::computeNumSignBits. #116321

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8 changes: 8 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -789,6 +789,14 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
MI.getOperand(3).getReg(), DemandedElts,
Depth + 1);
}
case TargetOpcode::G_SMIN:
case TargetOpcode::G_SMAX:
case TargetOpcode::G_UMIN:
case TargetOpcode::G_UMAX:
// TODO: Handle clamp pattern with number of sign bits for SMIN/SMAX.
return computeNumSignBitsMin(MI.getOperand(1).getReg(),
MI.getOperand(2).getReg(), DemandedElts,
Depth + 1);
case TargetOpcode::G_SADDO:
case TargetOpcode::G_SADDE:
case TargetOpcode::G_UADDO:
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,7 @@ body: |
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 8
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
Expand Down Expand Up @@ -66,8 +65,7 @@ body: |
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 16
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
Expand Down
9 changes: 3 additions & 6 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv64.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -31,8 +31,7 @@ body: |
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 8
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -72,8 +71,7 @@ body: |
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 16
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 16
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -108,8 +106,7 @@ body: |
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 32
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,7 @@ body: |
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMIN]], 8
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
; RV32ZBB-NEXT: $x10 = COPY [[SMIN]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
Expand Down Expand Up @@ -66,8 +65,7 @@ body: |
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMIN]], 16
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
; RV32ZBB-NEXT: $x10 = COPY [[SMIN]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
Expand Down
9 changes: 3 additions & 6 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv64.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -31,8 +31,7 @@ body: |
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 8
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -72,8 +71,7 @@ body: |
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 16
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 16
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down Expand Up @@ -108,8 +106,7 @@ body: |
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 32
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down
2 changes: 0 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
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Expand Up @@ -929,7 +929,6 @@ define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64ZBB-LABEL: min_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: min a0, a0, a1
; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: ret
%cmp = icmp slt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b
Expand Down Expand Up @@ -967,7 +966,6 @@ define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64ZBB-LABEL: max_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: max a0, a0, a1
; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: ret
%cmp = icmp sgt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b
Expand Down
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