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[mlir] Support ROCDL::ReadlaneOp #116593

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Merged
merged 2 commits into from
Nov 19, 2024
Merged

[mlir] Support ROCDL::ReadlaneOp #116593

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4910e2a
Support ROCDL::ReadlaneOp
knwng Nov 18, 2024
54f2f03
Use ROCDL_IntrOp to define ROCDL_ReadlaneOp; add smoke testing
knwng Nov 19, 2024
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15 changes: 15 additions & 0 deletions mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -197,6 +197,21 @@ def ROCDL_BallotOp :
let assemblyFormat = "$pred attr-dict `:` type($res)";
}

def ROCDL_ReadlaneOp : ROCDL_IntrOp<"readlane", [], [0], [AllTypesMatch<["res", "src0"]>], 1>,
Arguments<(ins LLVM_Type:$src0,
I32:$src1)> {
let results = (outs LLVM_Type:$res);
let summary = "Get the value in the specific lane.";

let description = [{
Get the value in lane `src1` from input `src0`.
}];

let assemblyFormat = [{
$src0 `,` $src1 attr-dict `:` `(` type($src0) `,` type($src1) `)` `->` type($res)
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You could optionally just use type($res) or type($src0), type($src1) here, but, ... it's a low-level intrinsic wrapper, it doesn't really matter.

Same for not having the parentheses.

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Actually, yeah, no, it's fine

}];
}

//===----------------------------------------------------------------------===//
// Thread index and Block index

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11 changes: 11 additions & 0 deletions mlir/test/Dialect/LLVMIR/rocdl.mlir
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Expand Up @@ -388,6 +388,17 @@ llvm.func @rocdl.s.wait.dscnt() {

// -----

llvm.func @rocdl.readlane(%src : f32) -> f32 {
%cst0 = llvm.mlir.constant(0 : i32) : i32

// CHECK-LABEL: rocdl.readlane
// CHECK: rocdl.readlane %{{.*}} %{{.*}}
%ret = rocdl.readlane %src, %cst0 : (f32, i32) -> f32
llvm.return %ret : f32
}

// -----

// expected-error@below {{attribute attached to unexpected op}}
func.func private @expected_llvm_func() attributes { rocdl.kernel }

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19 changes: 19 additions & 0 deletions mlir/test/Target/LLVMIR/rocdl.mlir
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Expand Up @@ -118,6 +118,25 @@ llvm.func @rocdl.ballot64(%pred : i1) -> i64 {
llvm.return %0 : i64
}

llvm.func @rocdl.readlane(%src0 : f32, %src1: f64, %src2: i32, %src3: vector<2 x f32>) -> f32 {
%idx = llvm.mlir.constant(0 : i32) : i32

// CHECK-LABEL: rocdl.readlane
// CHECK: call float @llvm.amdgcn.readlane.f32(float %{{.*}}, i32 0)
%0 = rocdl.readlane %src0, %idx : (f32, i32) -> f32

// CHECK: call double @llvm.amdgcn.readlane.f64(double %{{.*}}, i32 0)
%1 = rocdl.readlane %src1, %idx : (f64, i32) -> f64

// CHECK: call i32 @llvm.amdgcn.readlane.i32(i32 %{{.*}}, i32 0)
%2 = rocdl.readlane %src2, %idx : (i32, i32) -> i32

// CHECK: call <2 x float> @llvm.amdgcn.readlane.v2f32(<2 x float> %{{.*}}, i32 0)
%3 = rocdl.readlane %src3, %idx : (vector<2 x f32>, i32) -> vector<2 x f32>

llvm.return %0 : f32
}

llvm.func @rocdl.waitcnt() {
// CHECK-LABEL: rocdl.waitcnt
// CHECK-NEXT: call void @llvm.amdgcn.s.waitcnt(i32 0)
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