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[AArch64] Update predicate for FEXPA #116613

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Nov 19, 2024
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[AArch64] Update predicate for FEXPA #116613

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -971,7 +971,7 @@ let Predicates = [HasSVEorSME] in {
def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>;
} // End HasSVEorSME

let Predicates = [HasSVE] in {
let Predicates = [HasNonStreamingSVEorSME2p2] in {
defm FEXPA_ZZ : sve_int_bin_cons_misc_0_c_fexpa<"fexpa", int_aarch64_sve_fexpa_x>;
} // End HasSVE

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30 changes: 30 additions & 0 deletions llvm/test/CodeGen/AArch64/sve-intrinsics-fexpa.ll
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@@ -0,0 +1,30 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -force-streaming -mattr=+sme2p2 < %s | FileCheck %s

define <vscale x 8 x half> @fexpa_h(<vscale x 8 x i16> %a) {
; CHECK-LABEL: fexpa_h:
; CHECK: // %bb.0:
; CHECK-NEXT: fexpa z0.h, z0.h
; CHECK-NEXT: ret
%out = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %a)
ret <vscale x 8 x half> %out
}

define <vscale x 4 x float> @fexpa_s(<vscale x 4 x i32> %a) {
; CHECK-LABEL: fexpa_s:
; CHECK: // %bb.0:
; CHECK-NEXT: fexpa z0.s, z0.s
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %a)
ret <vscale x 4 x float> %out
}

define <vscale x 2 x double> @fexpa_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
; CHECK-LABEL: fexpa_d:
; CHECK: // %bb.0:
; CHECK-NEXT: fexpa z0.d, z0.d
; CHECK-NEXT: ret
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %a)
ret <vscale x 2 x double> %out
}
35 changes: 0 additions & 35 deletions llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
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Expand Up @@ -299,37 +299,6 @@ define <vscale x 2 x double> @fdivr_d(<vscale x 2 x i1> %pg, <vscale x 2 x doubl
ret <vscale x 2 x double> %out
}

;
; FEXPA
;

define <vscale x 8 x half> @fexpa_h(<vscale x 8 x i16> %a) {
; CHECK-LABEL: fexpa_h:
; CHECK: // %bb.0:
; CHECK-NEXT: fexpa z0.h, z0.h
; CHECK-NEXT: ret
%out = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %a)
ret <vscale x 8 x half> %out
}

define <vscale x 4 x float> @fexpa_s(<vscale x 4 x i32> %a) {
; CHECK-LABEL: fexpa_s:
; CHECK: // %bb.0:
; CHECK-NEXT: fexpa z0.s, z0.s
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %a)
ret <vscale x 4 x float> %out
}

define <vscale x 2 x double> @fexpa_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
; CHECK-LABEL: fexpa_d:
; CHECK: // %bb.0:
; CHECK-NEXT: fexpa z0.d, z0.d
; CHECK-NEXT: ret
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %a)
ret <vscale x 2 x double> %out
}

;
; FMAD
;
Expand Down Expand Up @@ -1668,10 +1637,6 @@ declare <vscale x 8 x half> @llvm.aarch64.sve.fdivr.nxv8f16(<vscale x 8 x i1>, <
declare <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
declare <vscale x 2 x double> @llvm.aarch64.sve.fdivr.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)

declare <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16>)
declare <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32>)
declare <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64>)

declare <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
declare <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
declare <vscale x 2 x double> @llvm.aarch64.sve.fmad.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
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8 changes: 5 additions & 3 deletions llvm/test/MC/AArch64/SVE/fexpa.s
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@@ -1,5 +1,7 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
Expand All @@ -12,17 +14,17 @@
fexpa z0.h, z31.h
// CHECK-INST: fexpa z0.h, z31.h
// CHECK-ENCODING: [0xe0,0xbb,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-ERROR: instruction requires: sve or sme2p2
// CHECK-UNKNOWN: 0460bbe0 <unknown>

fexpa z0.s, z31.s
// CHECK-INST: fexpa z0.s, z31.s
// CHECK-ENCODING: [0xe0,0xbb,0xa0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-ERROR: instruction requires: sve or sme2p2
// CHECK-UNKNOWN: 04a0bbe0 <unknown>

fexpa z0.d, z31.d
// CHECK-INST: fexpa z0.d, z31.d
// CHECK-ENCODING: [0xe0,0xbb,0xe0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-ERROR: instruction requires: sve or sme2p2
// CHECK-UNKNOWN: 04e0bbe0 <unknown>
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