[X86] Tidyup up AVX512 FPCLASS instruction naming #116661
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@llvm/pr-subscribers-backend-x86 Author: Simon Pilgrim (RKSimon) ChangesFPCLASS is a unary instruction with a immediate operand - update the naming to match similar instructions (e.g. VPSHUFD) by only using the source reg/mem and immediate in the instruction name Patch is 22.62 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/116661.diff 6 Files Affected:
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index 49e8bab4c0363d..70c71273d270f9 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -41,18 +41,18 @@ using namespace llvm;
CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
#define CASE_FPCLASS_PACKED(Inst, src) \
- CASE_AVX_INS_COMMON(Inst, Z, r##src) \
- CASE_AVX_INS_COMMON(Inst, Z256, r##src) \
- CASE_AVX_INS_COMMON(Inst, Z128, r##src) \
- CASE_MASK_INS_COMMON(Inst, Z, r##src)
+ CASE_AVX_INS_COMMON(Inst, Z, src##i) \
+ CASE_AVX_INS_COMMON(Inst, Z256, src##i) \
+ CASE_AVX_INS_COMMON(Inst, Z128, src##i) \
+ CASE_MASK_INS_COMMON(Inst, Z, src##i)
#define CASE_FPCLASS_PACKED_MEM(Inst) \
CASE_FPCLASS_PACKED(Inst, m) \
CASE_FPCLASS_PACKED(Inst, mb)
#define CASE_FPCLASS_SCALAR(Inst, src) \
- CASE_AVX_INS_COMMON(Inst, Z, r##src) \
- CASE_MASK_INS_COMMON(Inst, Z, r##src)
+ CASE_AVX_INS_COMMON(Inst, Z, src##i) \
+ CASE_MASK_INS_COMMON(Inst, Z, src##i)
#define CASE_PTERNLOG(Inst, src) \
CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 9480838e8a7bdf..ac5ef5b2e7b198 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -2457,13 +2457,13 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr,
X86FoldableSchedWrite sched, X86VectorVTInfo _,
Predicate prd> {
let Predicates = [prd], ExeDomain = _.ExeDomain, Uses = [MXCSR] in {
- def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
+ def ri : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
(ins _.RC:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set _.KRC:$dst,(X86Vfpclasss (_.VT _.RC:$src1),
(i32 timm:$src2)))]>,
Sched<[sched]>;
- def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
+ def rik : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
@@ -2471,7 +2471,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr,
(X86Vfpclasss_su (_.VT _.RC:$src1),
(i32 timm:$src2))))]>,
EVEX_K, Sched<[sched]>;
- def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+ def mi : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
(ins _.IntScalarMemOp:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
@@ -2479,7 +2479,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr,
(X86Vfpclasss (_.ScalarIntMemFrags addr:$src1),
(i32 timm:$src2)))]>,
Sched<[sched.Folded, sched.ReadAfterFold]>;
- def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+ def mik : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
(ins _.KRCWM:$mask, _.IntScalarMemOp:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
@@ -2497,13 +2497,13 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
X86FoldableSchedWrite sched, X86VectorVTInfo _,
string mem, list<Register> _Uses = [MXCSR]>{
let ExeDomain = _.ExeDomain, Uses = _Uses in {
- def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
+ def ri : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
(ins _.RC:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set _.KRC:$dst,(X86Vfpclass (_.VT _.RC:$src1),
(i32 timm:$src2)))]>,
Sched<[sched]>;
- def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
+ def rik : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
@@ -2511,7 +2511,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
(X86Vfpclass_su (_.VT _.RC:$src1),
(i32 timm:$src2))))]>,
EVEX_K, Sched<[sched]>;
- def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+ def mi : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
(ins _.MemOp:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#"{"#mem#"}"#
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
@@ -2519,7 +2519,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
(_.VT (_.LdFrag addr:$src1)),
(i32 timm:$src2)))]>,
Sched<[sched.Folded, sched.ReadAfterFold]>;
- def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+ def mik : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#"{"#mem#"}"#
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
@@ -2527,7 +2527,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
(_.VT (_.LdFrag addr:$src1)),
(i32 timm:$src2))))]>,
EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>;
- def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+ def mbi : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
(ins _.ScalarMemOp:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#"\t{$src2, ${src1}"#
_.BroadcastStr#", $dst|$dst, ${src1}"
@@ -2536,7 +2536,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
(_.VT (_.BroadcastLdFrag addr:$src1)),
(i32 timm:$src2)))]>,
EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
- def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
+ def mbik : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
(ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
OpcodeStr#_.Suffix#"\t{$src2, ${src1}"#
_.BroadcastStr#", $dst {${mask}}|$dst {${mask}}, ${src1}"#
@@ -2551,21 +2551,21 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
// the memory form.
def : InstAlias<OpcodeStr#_.Suffix#mem#
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- (!cast<Instruction>(NAME#"rr")
+ (!cast<Instruction>(NAME#"ri")
_.KRC:$dst, _.RC:$src1, i32u8imm:$src2), 0, "att">;
def : InstAlias<OpcodeStr#_.Suffix#mem#
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
- (!cast<Instruction>(NAME#"rrk")
+ (!cast<Instruction>(NAME#"rik")
_.KRC:$dst, _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2), 0, "att">;
def : InstAlias<OpcodeStr#_.Suffix#mem#
"\t{$src2, ${src1}"#_.BroadcastStr#", $dst|$dst, ${src1}"#
_.BroadcastStr#", $src2}",
- (!cast<Instruction>(NAME#"rmb")
+ (!cast<Instruction>(NAME#"mbi")
_.KRC:$dst, _.ScalarMemOp:$src1, i32u8imm:$src2), 0, "att">;
def : InstAlias<OpcodeStr#_.Suffix#mem#
"\t{$src2, ${src1}"#_.BroadcastStr#", $dst {${mask}}|"
"$dst {${mask}}, ${src1}"#_.BroadcastStr#", $src2}",
- (!cast<Instruction>(NAME#"rmbk")
+ (!cast<Instruction>(NAME#"mbik")
_.KRC:$dst, _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2), 0, "att">;
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 3af3aa838159d1..8551531b1b2671 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -7797,8 +7797,8 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
case X86::VFIXUPIMMSSZrri:
case X86::VFIXUPIMMSSZrrik:
case X86::VFIXUPIMMSSZrrikz:
- case X86::VFPCLASSSSZrr:
- case X86::VFPCLASSSSZrrk:
+ case X86::VFPCLASSSSZri:
+ case X86::VFPCLASSSSZrik:
case X86::VGETEXPSSZr:
case X86::VGETEXPSSZrk:
case X86::VGETEXPSSZrkz:
@@ -7966,8 +7966,8 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
case X86::VFIXUPIMMSDZrri:
case X86::VFIXUPIMMSDZrrik:
case X86::VFIXUPIMMSDZrrikz:
- case X86::VFPCLASSSDZrr:
- case X86::VFPCLASSSDZrrk:
+ case X86::VFPCLASSSDZri:
+ case X86::VFPCLASSSDZrik:
case X86::VGETEXPSDZr:
case X86::VGETEXPSDZrk:
case X86::VGETEXPSDZrkz:
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index a5051d932d4e21..18000d3b3c8ed0 100644
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -861,8 +861,8 @@ def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)kk",
"VCMPPD(Z|Z128|Z256)rri",
"VCMPPS(Z|Z128|Z256)rri",
"VCMP(SD|SS)Zrr",
- "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
- "VFPCLASS(SD|SS)Zrr",
+ "VFPCLASS(PD|PS)(Z|Z128|Z256)ri",
+ "VFPCLASS(SD|SS)Zri",
"VPCMPB(Z|Z128|Z256)rri",
"VPCMPD(Z|Z128|Z256)rri",
"VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
@@ -1705,8 +1705,8 @@ def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm,
VPMOVSXWDYrm,
VPMOVZXWDYrm)>;
def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
- "VFPCLASSSDZrm(b?)",
- "VFPCLASSSSZrm(b?)",
+ "VFPCLASSSDZm(b?)i",
+ "VFPCLASSSSZm(b?)i",
"(V?)PCMPGTQrm",
"VPERMI2DZ128rm(b?)",
"VPERMI2PDZ128rm(b?)",
@@ -1728,8 +1728,8 @@ def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> {
}
def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
"VCMP(SD|SS)Zrm",
- "VFPCLASSPDZ128rm(b?)",
- "VFPCLASSPSZ128rm(b?)",
+ "VFPCLASSPDZ128m(b?)i",
+ "VFPCLASSPSZ128m(b?)i",
"VPCMPBZ128rmi(b?)",
"VPCMPDZ128rmi(b?)",
"VPCMPEQ(B|D|Q|W)Z128rm(b?)",
@@ -1793,8 +1793,8 @@ def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> {
}
def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
"VCMPPS(Z|Z256)rm(b?)i",
- "VFPCLASSPD(Z|Z256)rm(b?)",
- "VFPCLASSPS(Z|Z256)rm(b?)",
+ "VFPCLASSPD(Z|Z256)m(b?)i",
+ "VFPCLASSPS(Z|Z256)m(b?)i",
"VPCMPB(Z|Z256)rmi(b?)",
"VPCMPD(Z|Z256)rmi(b?)",
"VPCMPEQB(Z|Z256)rm(b?)",
diff --git a/llvm/lib/Target/X86/X86SchedSapphireRapids.td b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
index 0545f9b7f4c00e..6727d166ab2a71 100644
--- a/llvm/lib/Target/X86/X86SchedSapphireRapids.td
+++ b/llvm/lib/Target/X86/X86SchedSapphireRapids.td
@@ -632,14 +632,14 @@ def : InstRW<[SPRWriteResGroup10], (instregex "^ADD_F(32|64)m$",
"^VPOPCNT(D|Q)Z128rmbk(z?)$")>;
def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
"^(V?)PCMPGTQrm$",
- "^VFPCLASSP(D|H|S)Z128rmb$",
+ "^VFPCLASSP(D|H|S)Z128mbi$",
"^VPACK(S|U)S(DW|WB)Z128rm$",
"^VPACK(S|U)SDWZ128rmb$",
"^VPM(AX|IN)(S|U)QZ128rm((b|k|bk|kz)?)$",
"^VPM(AX|IN)(S|U)QZ128rmbkz$",
"^VPMULTISHIFTQBZ128rm(b?)$")>;
-def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instrs VFPCLASSPHZ128rm)>;
-def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S)Z((256)?)rm$",
+def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instrs VFPCLASSPHZ128mi)>;
+def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S)Z((256)?)mi$",
"^VPERM(I|T)2(D|Q|PS)Z128rm((b|k|bk|kz)?)$",
"^VPERM(I|T)2(D|Q|PS)Z128rmbkz$",
"^VPERM(I|T)2PDZ128rm((b|k|bk|kz)?)$",
@@ -670,8 +670,8 @@ def : InstRW<[SPRWriteResGroup12], (instregex "^ADD_F(P?)rST0$",
"^VCMPP(D|H|S)Z(128|256)rri(k?)$",
"^VCMPS(D|H|S)Zrri$",
"^VCMPS(D|H|S)Zrr(b?)i_Int(k?)$",
- "^VFPCLASSP(D|H|S)Z(128|256)rr(k?)$",
- "^VFPCLASSS(D|H|S)Zrr(k?)$",
+ "^VFPCLASSP(D|H|S)Z(128|256)ri(k?)$",
+ "^VFPCLASSS(D|H|S)Zri(k?)$",
"^VPACK(S|U)S(DW|WB)Yrr$",
"^VPACK(S|U)S(DW|WB)Z(128|256)rr$",
"^VPALIGNRZ(128|256)rrik(z?)$",
@@ -1697,8 +1697,8 @@ def : InstRW<[SPRWriteResGroup134], (instregex "^VPBROADCAST(BY|WZ)rm$",
"^VPBROADCAST(B|W)Z256rm$",
"^VPBROADCAST(BZ|WY)rm$")>;
def : InstRW<[SPRWriteResGroup134, ReadAfterLd], (instrs MMX_PINSRWrmi)>;
-def : InstRW<[SPRWriteResGroup134, ReadAfterVecXLd], (instregex "^VFPCLASSP(D|S)Z128rm$")>;
-def : InstRW<[SPRWriteResGroup134, ReadAfterVecLd], (instregex "^VFPCLASSS(D|H|S)Zrm$")>;
+def : InstRW<[SPRWriteResGroup134, ReadAfterVecXLd], (instregex "^VFPCLASSP(D|S)Z128mi$")>;
+def : InstRW<[SPRWriteResGroup134, ReadAfterVecLd], (instregex "^VFPCLASSS(D|H|S)Zmi$")>;
def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instregex "^VPALIGNR(Y|Z256)rmi$")>;
def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instrs VPSHUFBZrm)>;
@@ -2659,7 +2659,7 @@ def : InstRW<[SPRWriteResGroup258], (instregex "^VPBROADCAST(B|W)Z128rmk(z?)$",
def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((256)?)rm(bi|ik)$",
"^VALIGN(D|Q)Z((256)?)rmbik(z?)$",
"^VALIGN(D|Q)Z((256)?)rmi((kz)?)$",
- "^VFPCLASSP(D|H|S)Z((256)?)rmb$",
+ "^VFPCLASSP(D|H|S)Z((256)?)mbi$",
"^VPACK(S|U)S(DW|WB)(Y|Z)rm$",
"^VPACK(S|U)S(DW|WB)Z256rm$",
"^VPACK(S|U)SDWZ((256)?)rmb$",
@@ -2724,7 +2724,7 @@ def SPRWriteResGroup263 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
}
def : InstRW<[SPRWriteResGroup263, ReadAfterVecXLd], (instregex "^VCMPP(D|H|S)Z128rm(bi|ik)$",
"^VCMPP(D|H|S)Z128rm(i|bik)$",
- "^VFPCLASSP(D|H|S)Z128rm(b?)k$",
+ "^VFPCLASSP(D|H|S)Z128m(b?)ik$",
"^VPCMP(B|D|Q|W|UD|UQ|UW)Z128rmi(k?)$",
"^VPCMP(D|Q|UQ)Z128rmib(k?)$",
"^VPCMP(EQ|GT)(B|D|Q|W)Z128rm(k?)$",
@@ -2735,7 +2735,7 @@ def : InstRW<[SPRWriteResGroup263, ReadAfterVecXLd], (instregex "^VCMPP(D|H|S)Z1
"^VPTEST(N?)M(D|Q)Z128rmb(k?)$")>;
def : InstRW<[SPRWriteResGroup263, ReadAfterVecYLd], (instregex "^VCMPP(D|H|S)Z((256)?)rm(bi|ik)$",
"^VCMPP(D|H|S)Z((256)?)rm(i|bik)$",
- "^VFPCLASSP(D|H|S)Z((256)?)rm(b?)k$",
+ "^VFPCLASSP(D|H|S)Z((256)?)m(b?)ik$",
"^VPCMP(B|D|Q|W|UD|UQ|UW)Z((256)?)rmi(k?)$",
"^VPCMP(D|Q|UQ)Z((256)?)rmib(k?)$",
"^VPCMP(EQ|GT)(B|D|Q|W)Z((256)?)rm(k?)$",
@@ -2746,7 +2746,7 @@ def : InstRW<[SPRWriteResGroup263, ReadAfterVecYLd], (instregex "^VCMPP(D|H|S)Z(
"^VPTEST(N?)M(D|Q)Z((256)?)rmb(k?)$")>;
def : InstRW<[SPRWriteResGroup263, ReadAfterVecLd], (instregex "^VCMPS(D|H|S)Zrmi$",
"^VCMPS(D|H|S)Zrmi_Int(k?)$",
- "^VFPCLASSS(D|H|S)Zrmk$")>;
+ "^VFPCLASSS(D|H|S)Zmik$")>;
def SPRWriteResGroup264 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
let Latency = 10;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index e733d9ac74dd84..2f9c6133eaa2d7 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -846,8 +846,8 @@ def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)kk",
"VCMPPD(Z|Z128|Z256)rri",
"VCMPPS(Z|Z128|Z256)rri",
"VCMP(SD|SS)Zrr",
- "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
- ...
[truncated]
|
You can test this locally with the following command:git-clang-format --diff d4f2b71c3fd89da4dbdec0091a97a6a2c411145d 830fe9632f71be1e88ce8a76a72810ca4496e11b --extensions cpp,inc -- llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp llvm/lib/Target/X86/X86InstrInfo.cpp llvm/test/TableGen/x86-fold-tables.incView the diff from clang-format here.diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index 70c71273d2..d90467982b 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -40,18 +40,18 @@ using namespace llvm;
CASE_MASK_INS_COMMON(Inst, Suffix, src) \
CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
-#define CASE_FPCLASS_PACKED(Inst, src) \
- CASE_AVX_INS_COMMON(Inst, Z, src##i) \
- CASE_AVX_INS_COMMON(Inst, Z256, src##i) \
- CASE_AVX_INS_COMMON(Inst, Z128, src##i) \
+#define CASE_FPCLASS_PACKED(Inst, src) \
+ CASE_AVX_INS_COMMON(Inst, Z, src##i) \
+ CASE_AVX_INS_COMMON(Inst, Z256, src##i) \
+ CASE_AVX_INS_COMMON(Inst, Z128, src##i) \
CASE_MASK_INS_COMMON(Inst, Z, src##i)
#define CASE_FPCLASS_PACKED_MEM(Inst) \
CASE_FPCLASS_PACKED(Inst, m) \
CASE_FPCLASS_PACKED(Inst, mb)
-#define CASE_FPCLASS_SCALAR(Inst, src) \
- CASE_AVX_INS_COMMON(Inst, Z, src##i) \
+#define CASE_FPCLASS_SCALAR(Inst, src) \
+ CASE_AVX_INS_COMMON(Inst, Z, src##i) \
CASE_MASK_INS_COMMON(Inst, Z, src##i)
#define CASE_PTERNLOG(Inst, src) \
|
|
Need to update TableGen/x86-fold-tables.td |
FPCLASS is a unary instruction with a immediate operand - update the naming to match similar instructions (e.g. VPSHUFD) by only using the source reg/mem and immediate in the instruction name
RKSimon
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FPCLASS is a unary instruction with a immediate operand - update the naming to match similar instructions (e.g. VPSHUFD) by only using the source reg/mem and immediate in the instruction name