[Thumb2][ARMAsmParser] Fix processing of t2{LDR,STR}{*}_{PRE,POST}_imm when changing to its concrete form

[bzEq]

t2{LDR,STR}{*}_{PRE,POST}_imm is pseudo instruction and is expected to be t2{LDR,STR}{*}_{PRE,POST}. During building the new MCInst of t2{LDR,STR}{*}_{PRE,POST}, the order of operands looks incorrect.

Fixes #97020.

[llvmbot]

@llvm/pr-subscribers-backend-arm

Author: Kai Luo (bzEq)

Changes

t2STR_POST_imm is pseudo instruction and is expected to be t2STR_POST. During building the new MCInst of t2STR_POST, the order looks incorrect.

Fixes #97020.

---

Full diff: https://github.com/llvm/llvm-project/pull/116757.diff

2 Files Affected:

• (modified) llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (+14-4)
• (added) llvm/test/tools/llvm-mca/ARM/m4-strw.s (+35)

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0dc637fc08aca3..99b813473bb9d5 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -9061,11 +9061,9 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
     return true;
   }
   // Aliases for imm syntax of STR instructions.
-  case ARM::t2STR_PRE_imm:
-  case ARM::t2STR_POST_imm: {
+  case ARM::t2STR_PRE_imm: {
     MCInst TmpInst;
-    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE
-                                                             : ARM::t2STR_POST);
+    TmpInst.setOpcode(ARM::t2STR_PRE);
     TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
     TmpInst.addOperand(Inst.getOperand(0)); // Rt
     TmpInst.addOperand(Inst.getOperand(1)); // Rn
@@ -9074,6 +9072,18 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
     Inst = TmpInst;
     return true;
   }
+  case ARM::t2STR_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::t2STR_POST);
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    TmpInst.addOperand(Inst.getOperand(4));
+    Inst = TmpInst;
+    return true;
+  }
   // Aliases for imm syntax of LDRB instructions.
   case ARM::t2LDRB_OFFSET_imm: {
     MCInst TmpInst;
diff --git a/llvm/test/tools/llvm-mca/ARM/m4-strw.s b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
new file mode 100644
index 00000000000000..11d3fcf9a75778
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s
+str.w r1, [r0], #16
+
+# CHECK:      Iterations:        100
+# CHECK-NEXT: Instructions:      100
+# CHECK-NEXT: Total Cycles:      101
+# CHECK-NEXT: Total uOps:        100
+
+# CHECK:      Dispatch Width:    1
+# CHECK-NEXT: uOps Per Cycle:    0.99
+# CHECK-NEXT: IPC:               0.99
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      1     1.00           *            str	r1, [r0], #16
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - M4Unit
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]
+# CHECK-NEXT: 1.00
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    Instructions:
+# CHECK-NEXT: 1.00   str	r1, [r0], #16

[davemgreen]

Can we make sure that pre-inc works at the same time?
https://godbolt.org/z/YPrxcGsjf

[ostannard]

These adjacent cases in that switch statement look like they have the same bug, and should be fixed at the same time:

t2LDR_PRE_imm
t2LDR_POST_imm
t2LDRB_PRE_imm
t2LDRB_POST_imm
t2STRB_PRE_imm
t2STRB_POST_imm
t2LDRH_PRE_imm
t2LDRH_POST_imm
t2STRH_PRE_imm
t2STRH_POST_imm
t2LDRSB_PRE_imm
t2LDRSB_POST_imm
t2LDRSH_PRE_imm
t2LDRSH_POST_imm

[ostannard]

LGTM, thanks!