Skip to content

[SandboxVec][SeedCollector] Reject non-simple memory ops for memory seeds #116891

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Nov 20, 2024
Merged

[SandboxVec][SeedCollector] Reject non-simple memory ops for memory seeds #116891

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
212f64c
Reject non-simple memory ops for memory seeds, but continue testing
Sterling-Augustine Nov 19, 2024
594d033
Address comments
Sterling-Augustine Nov 20, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -140,8 +140,8 @@ LLVM_DUMP_METHOD void SeedContainer::dump() const { print(dbgs()); }
#endif // NDEBUG

template <typename LoadOrStoreT> static bool isValidMemSeed(LoadOrStoreT *LSI) {
if (LSI->isSimple())
return true;
if (!LSI->isSimple())
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is there any test for cases where the LoadOrStoreT is simple, but one of the later checks fails?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

added

return false;
auto *Ty = Utils::getExpectedType(LSI);
// Omit types that are architecturally unvectorizable
if (Ty->isX86_FP80Ty() || Ty->isPPC_FP128Ty())
Expand Down
59 changes: 55 additions & 4 deletions llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SeedCollectorTest.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -394,12 +394,16 @@ define void @foo(ptr noalias %ptr, float %val) {

TEST_F(SeedBundleTest, VectorStores) {
parseIR(C, R"IR(
define void @foo(ptr noalias %ptr, <2 x float> %val) {
define void @foo(ptr noalias %ptr, <2 x float> %val0, i64 %val1) {
bb:
%ptr0 = getelementptr float, ptr %ptr, i32 0
%ptr1 = getelementptr float, ptr %ptr, i32 1
store <2 x float> %val, ptr %ptr1
store <2 x float> %val, ptr %ptr0
%ptr2 = getelementptr i64, ptr %ptr, i32 2
store <2 x float> %val0, ptr %ptr1
store <2 x float> %val0, ptr %ptr0
store atomic i64 %val1, ptr %ptr2 unordered, align 8
store volatile i64 %val1, ptr %ptr2

ret void
}
)IR");
Expand All @@ -418,14 +422,16 @@ define void @foo(ptr noalias %ptr, <2 x float> %val) {
sandboxir::SeedCollector SC(&*BB, SE);

// Find the stores
auto It = std::next(BB->begin(), 2);
auto It = std::next(BB->begin(), 3);
// StX with X as the order by offset in memory
auto *St1 = &*It++;
auto *St0 = &*It++;

auto StoreSeedsRange = SC.getStoreSeeds();
EXPECT_EQ(range_size(StoreSeedsRange), 1u);
auto &SB = *StoreSeedsRange.begin();
// isValidMemSeed check: The atomic and volatile stores should not
// be included in the bundle, but the vector stores should be.
ExpectThatElementsAre(SB, {St0, St1});
}

Expand Down Expand Up @@ -466,5 +472,50 @@ define void @foo(ptr noalias %ptr, float %v, <2 x float> %val) {
auto StoreSeedsRange = SC.getStoreSeeds();
EXPECT_EQ(range_size(StoreSeedsRange), 1u);
auto &SB = *StoreSeedsRange.begin();
// isValidMemSeedCheck here: all of the three stores should be included.
ExpectThatElementsAre(SB, {St0, St1, St3});
}

TEST_F(SeedBundleTest, VectorLoads) {
parseIR(C, R"IR(
define void @foo(ptr noalias %ptr, <2 x float> %val0) {
bb:
%ptr0 = getelementptr float, ptr %ptr, i32 0
%ptr1 = getelementptr float, ptr %ptr, i32 1
%r0 = load <2 x float>, ptr %ptr0
%r1 = load <2 x float>, ptr %ptr1
%r2 = load atomic i64, ptr %ptr0 unordered, align 8
%r3 = load volatile i64, ptr %ptr1
%r4 = load void()*, ptr %ptr1

ret void
}
)IR");
Function &LLVMF = *M->getFunction("foo");
DominatorTree DT(LLVMF);
TargetLibraryInfoImpl TLII;
TargetLibraryInfo TLI(TLII);
DataLayout DL(M->getDataLayout());
LoopInfo LI(DT);
AssumptionCache AC(LLVMF);
ScalarEvolution SE(LLVMF, TLI, AC, DT, LI);

sandboxir::Context Ctx(C);
auto &F = *Ctx.createFunction(&LLVMF);
auto BB = F.begin();
sandboxir::SeedCollector SC(&*BB, SE);

// Find the loads
auto It = std::next(BB->begin(), 2);
// StX with X as the order by offset in memory
auto *Ld0 = cast<sandboxir::LoadInst>(&*It++);
auto *Ld1 = cast<sandboxir::LoadInst>(&*It++);

auto LoadSeedsRange = SC.getLoadSeeds();
EXPECT_EQ(range_size(LoadSeedsRange), 2u);
auto &SB = *LoadSeedsRange.begin();
// isValidMemSeed check: The atomic and volatile loads should not
// be included in the bundle, the vector stores should be, but the
// void-typed load should not.
ExpectThatElementsAre(SB, {Ld0, Ld1});
}
Loading