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[X86] Fix shuffle comment decoding for vinsertps immediate operand #117009

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Merged
merged 5 commits into from
Nov 21, 2024
Merged

[X86] Fix shuffle comment decoding for vinsertps immediate operand #117009

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7f91f1c
[X86] Fix decoding for vinsertps immediate operand
omern1 Nov 20, 2024
b4a5781
Add newline at EOF
omern1 Nov 20, 2024
48efccb
Address review comments
omern1 Nov 20, 2024
50554db
Add tests for sse and evex
omern1 Nov 21, 2024
2c55706
Add new line at EOF
omern1 Nov 21, 2024
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12 changes: 9 additions & 3 deletions llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1122,15 +1122,21 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::VINSERTPSrri:
case X86::VINSERTPSZrri:
Src2Name = getRegName(MI->getOperand(2).getReg());
[[fallthrough]];
DestName = getRegName(MI->getOperand(0).getReg());
Src1Name = getRegName(MI->getOperand(1).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask,
/*SrcIsMem=*/false);
break;

case X86::INSERTPSrmi:
case X86::VINSERTPSrmi:
case X86::VINSERTPSZrmi:
DestName = getRegName(MI->getOperand(0).getReg());
Src1Name = getRegName(MI->getOperand(1).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(), ShuffleMask,
/*SrcIsMem=*/true);
break;

case X86::MOVLHPSrr:
Expand Down
5 changes: 3 additions & 2 deletions llvm/lib/Target/X86/MCTargetDesc/X86ShuffleDecode.cpp
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Expand Up @@ -23,7 +23,8 @@

namespace llvm {

void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask,
bool SrcIsMem) {
// Defaults the copying the dest value.
ShuffleMask.push_back(0);
ShuffleMask.push_back(1);
Expand All @@ -33,7 +34,7 @@ void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
// Decode the immediate.
unsigned ZMask = Imm & 15;
unsigned CountD = (Imm >> 4) & 3;
unsigned CountS = (Imm >> 6) & 3;
unsigned CountS = SrcIsMem ? 0 : (Imm >> 6) & 3;

// CountS selects which input element to use.
unsigned InVal = 4 + CountS;
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/X86/MCTargetDesc/X86ShuffleDecode.h
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Expand Up @@ -28,7 +28,8 @@ template <typename T> class SmallVectorImpl;
enum { SM_SentinelUndef = -1, SM_SentinelZero = -2 };

/// Decode a 128-bit INSERTPS instruction as a v4f32 shuffle mask.
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask,
bool SrcIsMem);

// Insert the bottom Len elements from a second source into a vector starting at
// element Idx.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -5362,7 +5362,7 @@ static bool getTargetShuffleMask(SDValue N, bool AllowSentinelZero,
assert(N.getOperand(0).getValueType() == VT && "Unexpected value type");
assert(N.getOperand(1).getValueType() == VT && "Unexpected value type");
ImmN = N.getConstantOperandVal(N.getNumOperands() - 1);
DecodeINSERTPSMask(ImmN, Mask);
DecodeINSERTPSMask(ImmN, Mask, /*SrcIsMem=*/false);
IsUnary = IsFakeUnary = N.getOperand(0) == N.getOperand(1);
break;
case X86ISD::EXTRQI:
Expand Down
11 changes: 11 additions & 0 deletions llvm/test/MC/X86/vinsertps_decode.s
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@@ -0,0 +1,11 @@
# RUN: llvm-mc -triple x86_64-unknown-unknown %s | FileCheck %s

.intel_syntax

# CHECK: insertps $176, (%rax), %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
# CHECK: vinsertps $176, (%rax), %xmm2, %xmm2 # xmm2 = xmm2[0,1,2],mem[0]
# CHECK: vinsertps $176, (%rax), %xmm29, %xmm0 # xmm0 = xmm29[0,1,2],mem[0]

insertps xmm2, dword ptr [rax], 0x0B0
vinsertps xmm2,xmm2,dword ptr [rax],0x0B0
vinsertps xmm0,xmm29,dword ptr [rax],0x0B0
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