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[SystemZ] Use getSignedConstant() where necessary #117181

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Merged
merged 2 commits into from
Nov 25, 2024
Merged

[SystemZ] Use getSignedConstant() where necessary #117181

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166a39f
[SystemZ] Use getSignedConstant()
nikic Nov 21, 2024
e2ebadd
Adjust more places
nikic Nov 22, 2024
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7 changes: 4 additions & 3 deletions llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -671,7 +671,7 @@ void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
}

// Lower the displacement to a TargetConstant.
Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT);
Disp = CurDAG->getSignedTargetConstant(AM.Disp, SDLoc(Base), VT);
}

void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
Expand Down Expand Up @@ -2024,8 +2024,9 @@ SDValue SystemZDAGToDAGISel::expandSelectBoolean(SDNode *Node) {
CurDAG->getConstant(IPM.XORValue, DL, MVT::i32));

if (IPM.AddValue)
Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result,
CurDAG->getConstant(IPM.AddValue, DL, MVT::i32));
Result =
CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result,
CurDAG->getSignedConstant(IPM.AddValue, DL, MVT::i32));

EVT VT = Node->getValueType(0);
if (VT == MVT::i32 && IPM.Bit == 31) {
Expand Down
21 changes: 11 additions & 10 deletions llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
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Expand Up @@ -1444,15 +1444,15 @@ void SystemZTargetLowering::LowerAsmOperandForConstraint(
case 'K': // Signed 16-bit constant
if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (isInt<16>(C->getSExtValue()))
Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
Op.getValueType()));
Ops.push_back(DAG.getSignedTargetConstant(
C->getSExtValue(), SDLoc(Op), Op.getValueType()));
return;

case 'L': // Signed 20-bit displacement (on all targets we support)
if (auto *C = dyn_cast<ConstantSDNode>(Op))
if (isInt<20>(C->getSExtValue()))
Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
Op.getValueType()));
Ops.push_back(DAG.getSignedTargetConstant(
C->getSExtValue(), SDLoc(Op), Op.getValueType()));
return;

case 'M': // 0x7fffffff
Expand Down Expand Up @@ -2578,7 +2578,7 @@ static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
// Make sure that the second operand is an i32 with the right value.
if (C.Op1.getValueType() != MVT::i32 ||
Value != ConstOp1->getZExtValue())
C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
C.Op1 = DAG.getConstant((uint32_t)Value, DL, MVT::i32);
}

// Return true if Op is either an unextended load, or a load suitable
Expand Down Expand Up @@ -3410,7 +3410,7 @@ SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
}
if (Invert) {
SDValue Mask =
DAG.getSplatBuildVector(VT, DL, DAG.getConstant(-1, DL, MVT::i64));
DAG.getSplatBuildVector(VT, DL, DAG.getAllOnesConstant(DL, MVT::i64));
Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
}
if (Chain && Chain.getNode() != Cmp.getNode()) {
Expand Down Expand Up @@ -3571,7 +3571,7 @@ SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
// addition for it.
if (Offset != 0)
Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
DAG.getConstant(Offset, DL, PtrVT));
DAG.getSignedConstant(Offset, DL, PtrVT));

return Result;
}
Expand Down Expand Up @@ -3834,7 +3834,7 @@ SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
const auto *TFL = Subtarget.getFrameLowering<SystemZFrameLowering>();
int Offset = TFL->getReturnAddressOffset(MF);
SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, FrameAddr,
DAG.getConstant(Offset, DL, PtrVT));
DAG.getSignedConstant(Offset, DL, PtrVT));
return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr,
MachinePointerInfo());
}
Expand Down Expand Up @@ -4584,7 +4584,7 @@ static void getCSAddressAndShifts(SDValue Addr, SelectionDAG &DAG, SDLoc DL,

// Get the address of the containing word.
AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
DAG.getConstant(-4, DL, PtrVT));
DAG.getSignedConstant(-4, DL, PtrVT));

// Get the number of bits that the word must be rotated left in order
// to bring the field to the top bits of a GR32.
Expand Down Expand Up @@ -4623,7 +4623,8 @@ SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
Opcode = SystemZISD::ATOMIC_LOADW_ADD;
Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
Src2 = DAG.getSignedConstant(-Const->getSExtValue(), DL,
Src2.getValueType());
}

SDValue AlignedAddr, BitShift, NegBitShift;
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/SystemZ/SystemZOperands.td
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Expand Up @@ -220,8 +220,8 @@ def NEGLF32 : SDNodeXForm<imm, [{

// Truncate an immediate to a 8-bit signed quantity.
def SIMM8 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
MVT::i64);
return CurDAG->getSignedTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
MVT::i64);
}]>;

// Truncate an immediate to a 8-bit unsigned quantity.
Expand All @@ -244,14 +244,14 @@ def UIMM12 : SDNodeXForm<imm, [{

// Truncate an immediate to a 16-bit signed quantity.
def SIMM16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
MVT::i64);
return CurDAG->getSignedTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
MVT::i64);
}]>;

// Negate and then truncate an immediate to a 16-bit signed quantity.
def NEGSIMM16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int16_t(-N->getZExtValue()), SDLoc(N),
MVT::i64);
return CurDAG->getSignedTargetConstant(int16_t(-N->getZExtValue()), SDLoc(N),
MVT::i64);
}]>;

// Truncate an immediate to a 16-bit unsigned quantity.
Expand All @@ -268,8 +268,8 @@ def SIMM32 : SDNodeXForm<imm, [{

// Negate and then truncate an immediate to a 32-bit unsigned quantity.
def NEGSIMM32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(int32_t(-N->getZExtValue()), SDLoc(N),
MVT::i64);
return CurDAG->getSignedTargetConstant(int32_t(-N->getZExtValue()), SDLoc(N),
MVT::i64);
}]>;

// Truncate an immediate to a 32-bit unsigned quantity.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
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Expand Up @@ -53,7 +53,7 @@ static SDValue emitMemMemReg(SelectionDAG &DAG, const SDLoc &DL, unsigned Op,
int64_t Adj = getMemMemLenAdj(Op);
SDValue LenAdj = DAG.getNode(ISD::ADD, DL, MVT::i64,
DAG.getZExtOrTrunc(Size, DL, MVT::i64),
DAG.getConstant(0 - Adj, DL, MVT::i64));
DAG.getSignedConstant(0 - Adj, DL, MVT::i64));
return createMemMemNode(DAG, DL, Op, Chain, Dst, Src, LenAdj, Byte);
}

Expand Down
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