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[SelectionDAG] Fix some SDNode type mismatches between *.td files and ISel #117375

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Merged
merged 1 commit into from
Nov 22, 2024
Merged

[SelectionDAG] Fix some SDNode type mismatches between *.td files and ISel #117375

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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARC/ARCInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -55,8 +55,7 @@ def ARCcmp : SDNode<"ARCISD::CMP", SDT_ARCcmptst, [SDNPOutGlue]>;
def ARCcmov : SDNode<"ARCISD::CMOV", SDT_ARCcmov, [SDNPInGlue]>;

// Conditional Branch
def ARCbrcc : SDNode<"ARCISD::BRcc", SDT_ARCbrcc,
[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
def ARCbrcc : SDNode<"ARCISD::BRcc", SDT_ARCbrcc, [SDNPHasChain, SDNPInGlue]>;

// Direct Call
def ARCBranchLink : SDNode<"ARCISD::BL",SDT_ARCBranchLink,
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6 changes: 2 additions & 4 deletions llvm/lib/Target/AVR/AVRISelLowering.cpp
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Expand Up @@ -890,10 +890,9 @@ SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue TargetCC;
SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);

SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};

return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
return DAG.getNode(AVRISD::SELECT_CC, dl, Op.getValueType(), Ops);
}

SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
Expand All @@ -907,10 +906,9 @@ SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {

SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};

return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
return DAG.getNode(AVRISD::SELECT_CC, DL, Op.getValueType(), Ops);
}

SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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3 changes: 1 addition & 2 deletions llvm/lib/Target/BPF/BPFISelLowering.cpp
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Expand Up @@ -696,10 +696,9 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
NegateCC(LHS, RHS, CC);

SDValue TargetCC = DAG.getConstant(CC, DL, LHS.getValueType());
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};

return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
return DAG.getNode(BPFISD::SELECT_CC, DL, Op.getValueType(), Ops);
}

const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
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2 changes: 1 addition & 1 deletion llvm/lib/Target/BPF/BPFInstrInfo.td
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Expand Up @@ -44,7 +44,7 @@ def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
[SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;

def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC>;
def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
def BPFmemcpy : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY,
[SDNPHasChain, SDNPInGlue, SDNPOutGlue,
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14 changes: 5 additions & 9 deletions llvm/lib/Target/Lanai/LanaiISelLowering.cpp
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Expand Up @@ -873,8 +873,7 @@ SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {

LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
SDValue Glue =
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);
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This isn't glue, but does look like it's unused according to the profile definition

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I've updated the description and comment message to accommodate for this.


return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
TargetCC, Glue);
Expand Down Expand Up @@ -973,8 +972,7 @@ SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {

LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
SDValue Glue =
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);

return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Glue);
}
Expand All @@ -990,12 +988,10 @@ SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,

LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
SDValue Glue =
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);

SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
Glue);
return DAG.getNode(LanaiISD::SELECT_CC, DL, Op.getValueType(), TrueV, FalseV,
TargetCC, Glue);
}

SDValue LanaiTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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7 changes: 3 additions & 4 deletions llvm/lib/Target/M68k/M68kISelLowering.cpp
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Expand Up @@ -2399,8 +2399,8 @@ SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
// Block CopyFromReg so partial register stalls are avoided.
T1.getOpcode() != ISD::CopyFromReg &&
T2.getOpcode() != ISD::CopyFromReg) {
SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
SDValue Cmov =
DAG.getNode(M68kISD::CMOV, DL, T1.getValueType(), T2, T1, CC, Cond);
return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
}
}
Expand All @@ -2418,9 +2418,8 @@ SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {

// M68kISD::CMOV means set the result (which is operand 1) to the RHS if
// condition is true.
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {Op2, Op1, CC, Cond};
return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
return DAG.getNode(M68kISD::CMOV, DL, Op.getValueType(), Ops);
}

/// Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Sparc/SparcInstrInfo.td
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Expand Up @@ -280,7 +280,7 @@ def SPbpicc : SDNode<"SPISD::BPICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPbpxcc : SDNode<"SPISD::BPXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPbrfccv9 : SDNode<"SPISD::BRFCC_V9", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPbrreg : SDNode<"SPISD::BR_REG", SDTSPbrreg, [SDNPHasChain, SDNPInGlue]>;
def SPbrreg : SDNode<"SPISD::BR_REG", SDTSPbrreg, [SDNPHasChain]>;

def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
Expand All @@ -293,7 +293,7 @@ def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
def SPselectreg : SDNode<"SPISD::SELECT_REG", SDTSPselectreg, [SDNPInGlue]>;
def SPselectreg : SDNode<"SPISD::SELECT_REG", SDTSPselectreg>;

// These are target-independent nodes, but have target-specific formats.
def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
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