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AMDGPU: Use isWave[32|64] instead of comparing size value #117411

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Merged
merged 1 commit into from
Nov 23, 2024
Merged

AMDGPU: Use isWave[32|64] instead of comparing size value #117411

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16677,8 +16677,8 @@ SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false);
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
if (RC == &AMDGPU::VReg_1RegClass && !isDivergent)
return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass
: &AMDGPU::SReg_32RegClass;
return Subtarget->isWave64() ? &AMDGPU::SReg_64RegClass
: &AMDGPU::SReg_32RegClass;
if (!TRI->isSGPRClass(RC) && !isDivergent)
return TRI->getEquivalentSGPRClass(RC);
if (TRI->isSGPRClass(RC) && isDivergent)
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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -7703,8 +7703,8 @@ void SIInstrInfo::lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
// Insert a trivial select instead of creating a copy, because a copy from
// SCC would semantically mean just copying a single bit, but we may need
// the result to be a vector condition mask that needs preserving.
unsigned Opcode = (ST.getWavefrontSize() == 64) ? AMDGPU::S_CSELECT_B64
: AMDGPU::S_CSELECT_B32;
unsigned Opcode =
ST.isWave64() ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
auto NewSelect =
BuildMI(MBB, MII, DL, get(Opcode), NewCondReg).addImm(-1).addImm(0);
NewSelect->getOperand(3).setIsUndef(Cond.isUndef());
Expand Down Expand Up @@ -8716,7 +8716,7 @@ uint64_t SIInstrInfo::getScratchRsrcWords23() const {
}

// IndexStride = 64 / 32.
uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2;
uint64_t IndexStride = ST.isWave64() ? 3 : 2;
Rsrc23 |= IndexStride << AMDGPU::RSRC_INDEX_STRIDE_SHIFT;

// If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//

def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
def isWave32 : Predicate<"Subtarget->isWave32()">,
AssemblerPredicate <(all_of FeatureWavefrontSize32)>;
def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
def isWave64 : Predicate<"Subtarget->isWave64()">,
AssemblerPredicate <(all_of FeatureWavefrontSize64)>;

class AMDGPUMnemonicAlias<string From, string To, string VariantName = "">
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