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AMDGPU: Move default wavesize hack for disassembler #117422

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Merged
merged 1 commit into from
Nov 23, 2024
Merged

AMDGPU: Move default wavesize hack for disassembler #117422

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20 changes: 2 additions & 18 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -45,26 +45,10 @@ using namespace llvm;

using DecodeStatus = llvm::MCDisassembler::DecodeStatus;

static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI,
MCContext &Ctx) {
if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) &&
!STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) {
MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI);
// If there is no default wave size it must be a generation before gfx10,
// these have FeatureWavefrontSize64 in their definition already. For gfx10+
// set wave32 as a default.
STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32);
return STICopy;
}

return STI;
}

AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
MCContext &Ctx, MCInstrInfo const *MCII)
: MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII),
MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()),
TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
// ToDo: AMDGPUDisassembler supports only VI ISA.
if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
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17 changes: 16 additions & 1 deletion llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
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Expand Up @@ -77,7 +77,22 @@ static MCSubtargetInfo *
createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (TT.getArch() == Triple::r600)
return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);

MCSubtargetInfo *STI =
createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);

// FIXME: We should error for the default target.
if (!STI->hasFeature(AMDGPU::FeatureWavefrontSize64) &&
!STI->hasFeature(AMDGPU::FeatureWavefrontSize32)) {
// If there is no default wave size it must be a generation before gfx10,
// these have FeatureWavefrontSize64 in their definition already. For gfx10+
// set wave32 as a default.
STI->ToggleFeature(AMDGPU::isGFX10Plus(*STI)
? AMDGPU::FeatureWavefrontSize32
: AMDGPU::FeatureWavefrontSize64);
}

return STI;
}

static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
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5 changes: 3 additions & 2 deletions llvm/test/MC/AMDGPU/unknown-target-cpu.s
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@@ -1,4 +1,5 @@
// RUN: llvm-mc -triple=amdgcn -show-encoding < %s | FileCheck %s
// RUN: not llvm-mc -triple=amdgcn -show-encoding < %s | FileCheck %s
// RUN: not llvm-mc -triple=amdgcn -show-encoding -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
// RUN: llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding < %s | FileCheck %s

// CHECK: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c]
Expand All @@ -7,7 +8,7 @@ v_cmp_lt_f32 vcc, s2, v4
// CHECK: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
v_cndmask_b32 v1, v2, v3, vcc

// CHECK: v_mac_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0c,0xd2,0x03,0x0b,0x00,0x00]
// ERR: [[@LINE+1]]:1: error: instruction not supported on this GPU
v_mac_legacy_f32 v1, v3, s5

// CHECK: v_lshr_b32_e32 v0, v1, v2 ; encoding: [0x01,0x05,0x00,0x2a]
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