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[AMDGPU][AMDGPURegBankInfo] Map S_BUFFER_LOAD_XXX to its corresponding BUFFER_LOAD_XXX #117574

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Merged
merged 1 commit into from
Dec 16, 2024
Merged

[AMDGPU][AMDGPURegBankInfo] Map S_BUFFER_LOAD_XXX to its corresponding BUFFER_LOAD_XXX #117574

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38 changes: 28 additions & 10 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1330,6 +1330,24 @@ unsigned AMDGPURegisterBankInfo::setBufferOffsets(
return 0;
}

static unsigned getSBufferLoadCorrespondingBufferLoadOpcode(unsigned Opc) {
switch (Opc) {
case AMDGPU::G_AMDGPU_S_BUFFER_LOAD:
return AMDGPU::G_AMDGPU_BUFFER_LOAD;
case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE:
return AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE;
case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE:
return AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE;
case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT:
return AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT;
case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SSHORT:
return AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT;
default:
break;
}
llvm_unreachable("Unexpected s_buffer_load opcode");
}

bool AMDGPURegisterBankInfo::applyMappingSBufferLoad(
MachineIRBuilder &B, const OperandsMapper &OpdMapper) const {
MachineInstr &MI = OpdMapper.getMI();
Expand Down Expand Up @@ -1406,16 +1424,16 @@ bool AMDGPURegisterBankInfo::applyMappingSBufferLoad(
if (i != 0)
BaseMMO = MF.getMachineMemOperand(BaseMMO, MMOOffset + 16 * i, MemSize);

B.buildInstr(AMDGPU::G_AMDGPU_BUFFER_LOAD)
.addDef(LoadParts[i]) // vdata
.addUse(RSrc) // rsrc
.addUse(VIndex) // vindex
.addUse(VOffset) // voffset
.addUse(SOffset) // soffset
.addImm(ImmOffset + 16 * i) // offset(imm)
.addImm(0) // cachepolicy, swizzled buffer(imm)
.addImm(0) // idxen(imm)
.addMemOperand(MMO);
B.buildInstr(getSBufferLoadCorrespondingBufferLoadOpcode(MI.getOpcode()))
.addDef(LoadParts[i]) // vdata
.addUse(RSrc) // rsrc
.addUse(VIndex) // vindex
.addUse(VOffset) // voffset
.addUse(SOffset) // soffset
.addImm(ImmOffset + 16 * i) // offset(imm)
.addImm(0) // cachepolicy, swizzled buffer(imm)
.addImm(0) // idxen(imm)
.addMemOperand(MMO);
}

// TODO: If only the resource is a VGPR, it may be better to execute the
Expand Down
78 changes: 24 additions & 54 deletions llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -465,19 +465,12 @@ main_body:
}

define amdgpu_ps void @s_buffer_load_byte_sgpr_or_imm_offset_divergent(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) {
; DAG-LABEL: s_buffer_load_byte_sgpr_or_imm_offset_divergent:
; DAG: ; %bb.0: ; %main_body
; DAG-NEXT: buffer_load_i8 v2, v2, s[0:3], null offen
; DAG-NEXT: s_wait_loadcnt 0x0
; DAG-NEXT: global_store_b32 v[0:1], v2, off
; DAG-NEXT: s_endpgm
;
; GISEL-LABEL: s_buffer_load_byte_sgpr_or_imm_offset_divergent:
; GISEL: ; %bb.0: ; %main_body
; GISEL-NEXT: buffer_load_b32 v2, v2, s[0:3], null offen
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GISEL-NEXT: s_endpgm
; GCN-LABEL: s_buffer_load_byte_sgpr_or_imm_offset_divergent:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: buffer_load_i8 v2, v2, s[0:3], null offen
; GCN-NEXT: s_wait_loadcnt 0x0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
main_body:
%ld = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %src, i32 %offset, i32 0)
%sext = sext i8 %ld to i32
Expand Down Expand Up @@ -538,20 +531,12 @@ main_body:
}

define amdgpu_ps void @s_buffer_load_ubyte_sgpr_or_imm_offset_divergent(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) {
; DAG-LABEL: s_buffer_load_ubyte_sgpr_or_imm_offset_divergent:
; DAG: ; %bb.0: ; %main_body
; DAG-NEXT: buffer_load_u8 v2, v2, s[0:3], null offen
; DAG-NEXT: s_wait_loadcnt 0x0
; DAG-NEXT: global_store_b32 v[0:1], v2, off
; DAG-NEXT: s_endpgm
;
; GISEL-LABEL: s_buffer_load_ubyte_sgpr_or_imm_offset_divergent:
; GISEL: ; %bb.0: ; %main_body
; GISEL-NEXT: buffer_load_b32 v2, v2, s[0:3], null offen
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
; GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GISEL-NEXT: s_endpgm
; GCN-LABEL: s_buffer_load_ubyte_sgpr_or_imm_offset_divergent:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: buffer_load_u8 v2, v2, s[0:3], null offen
; GCN-NEXT: s_wait_loadcnt 0x0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
main_body:
%ld = call i8 @llvm.amdgcn.s.buffer.load.u8(<4 x i32> %src, i32 %offset, i32 0)
%zext = zext i8 %ld to i32
Expand Down Expand Up @@ -606,19 +591,12 @@ main_body:
}

define amdgpu_ps void @s_buffer_load_short_sgpr_or_imm_offset_divergent(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) {
; DAG-LABEL: s_buffer_load_short_sgpr_or_imm_offset_divergent:
; DAG: ; %bb.0: ; %main_body
; DAG-NEXT: buffer_load_i16 v2, v2, s[0:3], null offen
; DAG-NEXT: s_wait_loadcnt 0x0
; DAG-NEXT: global_store_b32 v[0:1], v2, off
; DAG-NEXT: s_endpgm
;
; GISEL-LABEL: s_buffer_load_short_sgpr_or_imm_offset_divergent:
; GISEL: ; %bb.0: ; %main_body
; GISEL-NEXT: buffer_load_b32 v2, v2, s[0:3], null offen
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GISEL-NEXT: s_endpgm
; GCN-LABEL: s_buffer_load_short_sgpr_or_imm_offset_divergent:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: buffer_load_i16 v2, v2, s[0:3], null offen
; GCN-NEXT: s_wait_loadcnt 0x0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
main_body:
%ld = call i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32> %src, i32 %offset, i32 0)
%sext = sext i16 %ld to i32
Expand Down Expand Up @@ -679,20 +657,12 @@ main_body:
}

define amdgpu_ps void @s_buffer_load_ushort_sgpr_or_imm_offset_divergent(<4 x i32> inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) {
; DAG-LABEL: s_buffer_load_ushort_sgpr_or_imm_offset_divergent:
; DAG: ; %bb.0: ; %main_body
; DAG-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen
; DAG-NEXT: s_wait_loadcnt 0x0
; DAG-NEXT: global_store_b32 v[0:1], v2, off
; DAG-NEXT: s_endpgm
;
; GISEL-LABEL: s_buffer_load_ushort_sgpr_or_imm_offset_divergent:
; GISEL: ; %bb.0: ; %main_body
; GISEL-NEXT: buffer_load_b32 v2, v2, s[0:3], null offen
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GISEL-NEXT: s_endpgm
; GCN-LABEL: s_buffer_load_ushort_sgpr_or_imm_offset_divergent:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen
; GCN-NEXT: s_wait_loadcnt 0x0
; GCN-NEXT: global_store_b32 v[0:1], v2, off
; GCN-NEXT: s_endpgm
main_body:
%ld = call i16 @llvm.amdgcn.s.buffer.load.u16(<4 x i32> %src, i32 %offset, i32 0)
%zext = zext i16 %ld to i32
Expand Down
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