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[RISCV] Rename some Feature* to Tune* #117966

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Merged
merged 1 commit into from
Nov 28, 2024
Merged

[RISCV] Rename some Feature* to Tune* #117966

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1388,10 +1388,10 @@ def FeatureUnalignedVectorMem
"true", "Has reasonably performant unaligned vector "
"loads and stores">;

def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
"UsePostRAScheduler", "true", "Schedule again after register allocation">;

def FeaturePredictableSelectIsExpensive
def TunePredictableSelectIsExpensive
: SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
"Prefer likely predicted branches over selects">;

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22 changes: 11 additions & 11 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,7 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",

defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll,
TuneShortForwardBranchOpt,
FeaturePostRAScheduler];
TunePostRAScheduler];
def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
SiFive7Model, SiFive7TuneFeatures>;

Expand Down Expand Up @@ -251,7 +251,7 @@ defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
TuneConditionalCompressedMoveFusion,
TuneLUIADDIFusion,
TuneAUIPCADDIFusion,
FeaturePostRAScheduler];
TunePostRAScheduler];

def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
!listconcat(RVA22U64Features,
Expand Down Expand Up @@ -300,7 +300,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
TuneAUIPCADDIFusion,
TuneNoSinkSplatOperands,
TuneVXRMPipelineFlush,
FeaturePostRAScheduler]>;
TunePostRAScheduler]>;

def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
SyntacoreSCR1Model,
Expand Down Expand Up @@ -329,7 +329,7 @@ def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
[TuneNoDefaultUnroll, TunePostRAScheduler]>;

def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
SyntacoreSCR3RV64Model,
Expand All @@ -340,7 +340,7 @@ def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
[TuneNoDefaultUnroll, TunePostRAScheduler]>;

def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
SyntacoreSCR4RV32Model,
Expand All @@ -352,7 +352,7 @@ def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
[TuneNoDefaultUnroll, TunePostRAScheduler]>;

def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
SyntacoreSCR4RV64Model,
Expand All @@ -365,7 +365,7 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
[TuneNoDefaultUnroll, TunePostRAScheduler]>;

def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
SyntacoreSCR5RV32Model,
Expand All @@ -378,7 +378,7 @@ def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
[TuneNoDefaultUnroll, TunePostRAScheduler]>;

def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
SyntacoreSCR5RV64Model,
Expand All @@ -391,7 +391,7 @@ def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
[TuneNoDefaultUnroll, TunePostRAScheduler]>;

def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
SyntacoreSCR7Model,
Expand All @@ -410,7 +410,7 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZbc,
FeatureStdExtZbs,
FeatureStdExtZkn],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
[TuneNoDefaultUnroll, TunePostRAScheduler]>;

def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
NoSchedModel,
Expand All @@ -432,7 +432,7 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
FeatureUnalignedVectorMem]),
[TuneNoDefaultUnroll,
TuneOptimizedZeroStrideLoad,
FeaturePostRAScheduler]>;
TunePostRAScheduler]>;

def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
NoSchedModel,
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ entry:
}

; Test has highly predictable select according to profile data,
; which should be transformed to a branch on cores with enabled FeaturePredictableSelectIsExpensive
; which should be transformed to a branch on cores with enabled TunePredictableSelectIsExpensive
define i32 @test2(i32 %a) {
; CHEAP-LABEL: test2:
; CHEAP: # %bb.0: # %entry
Expand Down