[RISCV][GISel] Add FCLASS to onlyUsesFP for register bank selection #118021
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-risc-v Author: Luke Quinn (lquinn2015) ChangesBug fix FCLASS instruction in RISCV. The bug is due the fact that FCLASS has an input float register and output GPR this caused reg bank select regression. To test i had to improve the MIR generate script to accept preprocess commands by using the common infra shared with update_llc_checks.py. I tested my file and another unrelated for compatibility. Let me know what I can improve :) @topperc POC Patch is 20.44 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/118021.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 829c0ac92c52a4..a082b188676661 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -151,6 +151,7 @@ bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
switch (MI.getOpcode()) {
case RISCV::G_FCVT_W_RV64:
case RISCV::G_FCVT_WU_RV64:
+ case RISCV::G_FCLASS:
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_FCMP:
@@ -326,19 +327,21 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// Use FPR64 for s64 loads on rv32.
if (GPRSize == 32 && Size.getFixedValue() == 64) {
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
- OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
+ OpdsMapping[0] = getFPValueMapping(Size);
break;
}
// Check if that load feeds fp instructions.
// In that case, we want the default mapping to be on FPR
// instead of blind map every scalar to GPR.
- if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI))
+ if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI)) {
// If we have at least one direct use in a FP instruction,
// assume this was a floating point load in the IR. If it was
// not, we would have had a bitcast before reaching that
// instruction.
- OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
+ OpdsMapping[0] = getFPValueMapping(Size);
+ break;
+ }
break;
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
index f74362298a6cb9..cc2a4212cdda65 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir
@@ -1,10 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
-# RUN: -o - | FileCheck %s --check-prefixes=CHECK
-# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \
-# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
-# RUN: -o - | FileCheck %s --check-prefixes=CHECK
+# RUN: sed 's/XLen/32/g' %s | llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs -x mir \
+# RUN: -o - | FileCheck %s --check-prefixes=CHECK-RV32
+# RUN: sed 's/XLen/64/g' %s | llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs -x mir \
+# RUN: -o - | FileCheck %s --check-prefixes=CHECK-RV64
---
name: fp_store_fp_def_f32
@@ -14,15 +14,25 @@ body: |
bb.1:
liveins: $x10, $f10_f, $f11_f
- ; CHECK-LABEL: name: fp_store_fp_def_f32
- ; CHECK: liveins: $x10, $f10_f, $f11_f
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY2]]
- ; CHECK-NEXT: G_STORE [[FADD]](s32), [[COPY]](p0) :: (store (s32))
- ; CHECK-NEXT: PseudoRET
+ ; CHECK-RV32-LABEL: name: fp_store_fp_def_f32
+ ; CHECK-RV32: liveins: $x10, $f10_f, $f11_f
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-RV32-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY2]]
+ ; CHECK-RV32-NEXT: G_STORE [[FADD]](s32), [[COPY]](p0) :: (store (s32))
+ ; CHECK-RV32-NEXT: PseudoRET
+ ;
+ ; CHECK-RV64-LABEL: name: fp_store_fp_def_f32
+ ; CHECK-RV64: liveins: $x10, $f10_f, $f11_f
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-RV64-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY2]]
+ ; CHECK-RV64-NEXT: G_STORE [[FADD]](s32), [[COPY]](p0) :: (store (s32))
+ ; CHECK-RV64-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(s32) = COPY $f10_f
%2:_(s32) = COPY $f11_f
@@ -39,15 +49,25 @@ body: |
bb.1:
liveins: $x10, $f10_d, $f11_d
- ; CHECK-LABEL: name: fp_store_fp_def_f64
- ; CHECK: liveins: $x10, $f10_d, $f11_d
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY1]], [[COPY2]]
- ; CHECK-NEXT: G_STORE [[FADD]](s64), [[COPY]](p0) :: (store (s64))
- ; CHECK-NEXT: PseudoRET
+ ; CHECK-RV32-LABEL: name: fp_store_fp_def_f64
+ ; CHECK-RV32: liveins: $x10, $f10_d, $f11_d
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-RV32-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY1]], [[COPY2]]
+ ; CHECK-RV32-NEXT: G_STORE [[FADD]](s64), [[COPY]](p0) :: (store (s64))
+ ; CHECK-RV32-NEXT: PseudoRET
+ ;
+ ; CHECK-RV64-LABEL: name: fp_store_fp_def_f64
+ ; CHECK-RV64: liveins: $x10, $f10_d, $f11_d
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-RV64-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY1]], [[COPY2]]
+ ; CHECK-RV64-NEXT: G_STORE [[FADD]](s64), [[COPY]](p0) :: (store (s64))
+ ; CHECK-RV64-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $f10_d
%2:_(s64) = COPY $f11_d
@@ -64,13 +84,21 @@ body: |
bb.1:
liveins: $x10, $f10_d
- ; CHECK-LABEL: name: fp_store_no_def_f64
- ; CHECK: liveins: $x10, $f10_d
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
- ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
- ; CHECK-NEXT: PseudoRET
+ ; CHECK-RV32-LABEL: name: fp_store_no_def_f64
+ ; CHECK-RV32: liveins: $x10, $f10_d
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-RV32-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
+ ; CHECK-RV32-NEXT: PseudoRET
+ ;
+ ; CHECK-RV64-LABEL: name: fp_store_no_def_f64
+ ; CHECK-RV64: liveins: $x10, $f10_d
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-RV64-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
+ ; CHECK-RV64-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $f10_d
G_STORE %1(s64), %0(p0) :: (store (s64))
@@ -85,15 +113,25 @@ body: |
bb.1:
liveins: $x10, $f10_f
- ; CHECK-LABEL: name: fp_load_fp_use_f32
- ; CHECK: liveins: $x10, $f10_f
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[COPY1]]
- ; CHECK-NEXT: $f10_f = COPY [[FADD]](s32)
- ; CHECK-NEXT: PseudoRET implicit $f10_f
+ ; CHECK-RV32-LABEL: name: fp_load_fp_use_f32
+ ; CHECK-RV32: liveins: $x10, $f10_f
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[COPY1]]
+ ; CHECK-RV32-NEXT: $f10_f = COPY [[FADD]](s32)
+ ; CHECK-RV32-NEXT: PseudoRET implicit $f10_f
+ ;
+ ; CHECK-RV64-LABEL: name: fp_load_fp_use_f32
+ ; CHECK-RV64: liveins: $x10, $f10_f
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[COPY1]]
+ ; CHECK-RV64-NEXT: $f10_f = COPY [[FADD]](s32)
+ ; CHECK-RV64-NEXT: PseudoRET implicit $f10_f
%0:_(p0) = COPY $x10
%1:_(s32) = COPY $f10_f
%2:_(s32) = G_LOAD %0(p0) :: (load (s32))
@@ -110,15 +148,25 @@ body: |
bb.1:
liveins: $x10, $f10_d
- ; CHECK-LABEL: name: fp_load_fp_use_f64
- ; CHECK: liveins: $x10, $f10_d
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[LOAD]], [[COPY1]]
- ; CHECK-NEXT: $f10_d = COPY [[FADD]](s64)
- ; CHECK-NEXT: PseudoRET implicit $f10_d
+ ; CHECK-RV32-LABEL: name: fp_load_fp_use_f64
+ ; CHECK-RV32: liveins: $x10, $f10_d
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[LOAD]], [[COPY1]]
+ ; CHECK-RV32-NEXT: $f10_d = COPY [[FADD]](s64)
+ ; CHECK-RV32-NEXT: PseudoRET implicit $f10_d
+ ;
+ ; CHECK-RV64-LABEL: name: fp_load_fp_use_f64
+ ; CHECK-RV64: liveins: $x10, $f10_d
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[LOAD]], [[COPY1]]
+ ; CHECK-RV64-NEXT: $f10_d = COPY [[FADD]](s64)
+ ; CHECK-RV64-NEXT: PseudoRET implicit $f10_d
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $f10_d
%2:_(s64) = G_LOAD %0(p0) :: (load (s64))
@@ -135,14 +183,23 @@ body: |
bb.1:
liveins: $x10, $f10_d
- ; CHECK-LABEL: name: fp_load_no_use_f64
- ; CHECK: liveins: $x10, $f10_d
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
- ; CHECK-NEXT: $f10_d = COPY [[LOAD]](s64)
- ; CHECK-NEXT: PseudoRET implicit $f10_d
+ ; CHECK-RV32-LABEL: name: fp_load_no_use_f64
+ ; CHECK-RV32: liveins: $x10, $f10_d
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; CHECK-RV32-NEXT: $f10_d = COPY [[LOAD]](s64)
+ ; CHECK-RV32-NEXT: PseudoRET implicit $f10_d
+ ;
+ ; CHECK-RV64-LABEL: name: fp_load_no_use_f64
+ ; CHECK-RV64: liveins: $x10, $f10_d
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; CHECK-RV64-NEXT: $f10_d = COPY [[LOAD]](s64)
+ ; CHECK-RV64-NEXT: PseudoRET implicit $f10_d
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $f10_d
%2:_(s64) = G_LOAD %0(p0) :: (load (s64))
@@ -158,15 +215,25 @@ body: |
bb.1:
liveins: $x10, $f10_h, $f11_h
- ; CHECK-LABEL: name: fp_store_fp_def_f16
- ; CHECK: liveins: $x10, $f10_h, $f11_h
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f11_h
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY1]], [[COPY2]]
- ; CHECK-NEXT: G_STORE [[FADD]](s16), [[COPY]](p0) :: (store (s16))
- ; CHECK-NEXT: PseudoRET
+ ; CHECK-RV32-LABEL: name: fp_store_fp_def_f16
+ ; CHECK-RV32: liveins: $x10, $f10_h, $f11_h
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-RV32-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY1]], [[COPY2]]
+ ; CHECK-RV32-NEXT: G_STORE [[FADD]](s16), [[COPY]](p0) :: (store (s16))
+ ; CHECK-RV32-NEXT: PseudoRET
+ ;
+ ; CHECK-RV64-LABEL: name: fp_store_fp_def_f16
+ ; CHECK-RV64: liveins: $x10, $f10_h, $f11_h
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-RV64-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY1]], [[COPY2]]
+ ; CHECK-RV64-NEXT: G_STORE [[FADD]](s16), [[COPY]](p0) :: (store (s16))
+ ; CHECK-RV64-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(s16) = COPY $f10_h
%2:_(s16) = COPY $f11_h
@@ -183,15 +250,25 @@ body: |
bb.1:
liveins: $x10, $f10_h
- ; CHECK-LABEL: name: fp_load_fp_use_f16
- ; CHECK: liveins: $x10, $f10_h
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[LOAD]], [[COPY1]]
- ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16)
- ; CHECK-NEXT: PseudoRET implicit $f10_h
+ ; CHECK-RV32-LABEL: name: fp_load_fp_use_f16
+ ; CHECK-RV32: liveins: $x10, $f10_h
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-RV32-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[LOAD]], [[COPY1]]
+ ; CHECK-RV32-NEXT: $f10_h = COPY [[FADD]](s16)
+ ; CHECK-RV32-NEXT: PseudoRET implicit $f10_h
+ ;
+ ; CHECK-RV64-LABEL: name: fp_load_fp_use_f16
+ ; CHECK-RV64: liveins: $x10, $f10_h
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-RV64-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[LOAD]], [[COPY1]]
+ ; CHECK-RV64-NEXT: $f10_h = COPY [[FADD]](s16)
+ ; CHECK-RV64-NEXT: PseudoRET implicit $f10_h
%0:_(p0) = COPY $x10
%1:_(s16) = COPY $f10_h
%2:_(s16) = G_LOAD %0(p0) :: (load (s16))
@@ -200,3 +277,49 @@ body: |
PseudoRET implicit $f10_h
...
+---
+name: fpclass
+legalized: true
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x10' }
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-RV32-LABEL: name: fpclass
+ ; CHECK-RV32: liveins: $x10
+ ; CHECK-RV32-NEXT: {{ $}}
+ ; CHECK-RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV32-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-RV32-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 927
+ ; CHECK-RV32-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; CHECK-RV32-NEXT: [[FCLASS:%[0-9]+]]:gprb(s32) = G_FCLASS [[LOAD]](s32)
+ ; CHECK-RV32-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[FCLASS]], [[C]]
+ ; CHECK-RV32-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
+ ; CHECK-RV32-NEXT: $x10 = COPY [[ICMP]](s32)
+ ; CHECK-RV32-NEXT: PseudoRET implicit $x10
+ ;
+ ; CHECK-RV64-LABEL: name: fpclass
+ ; CHECK-RV64: liveins: $x10
+ ; CHECK-RV64-NEXT: {{ $}}
+ ; CHECK-RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-RV64-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-RV64-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 927
+ ; CHECK-RV64-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0
+ ; CHECK-RV64-NEXT: [[FCLASS:%[0-9]+]]:gprb(s64) = G_FCLASS [[LOAD]](s32)
+ ; CHECK-RV64-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[FCLASS]], [[C]]
+ ; CHECK-RV64-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]]
+ ; CHECK-RV64-NEXT: $x10 = COPY [[ICMP]](s64)
+ ; CHECK-RV64-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_LOAD %0(p0) :: (load (s32))
+ %4:_(sXLen) = G_CONSTANT iXLen 927
+ %5:_(sXLen) = G_CONSTANT iXLen 0
+ %6:_(sXLen) = G_FCLASS %1(s32)
+ %7:_(sXLen) = G_AND %6, %4
+ %8:_(sXLen) = G_ICMP intpred(ne), %7(sXLen), %5
+ $x10 = COPY %8(sXLen)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/utils/update_mir_test_checks.py b/llvm/utils/update_mir_test_checks.py
index 86adf77714a119..0ab2191ac6d966 100755
--- a/llvm/utils/update_mir_test_checks.py
+++ b/llvm/utils/update_mir_test_checks.py
@@ -87,13 +87,14 @@ def __call__(self, args, ir):
class Run:
- def __init__(self, prefixes, cmd_args, triple):
+ def __init__(self, prefixes, cmd_args, preprocess_cmd, triple):
self.prefixes = prefixes
self.cmd_args = cmd_args
+ self.preprocess_cmd = preprocess_cmd
self.triple = triple
def __getitem__(self, index):
- return [self.prefixes, self.cmd_args, self.triple][index]
+ return [self.prefixes, self.cmd_args, self.preprocess_cmd, self.triple][index]
def log(msg, verbose=True):
@@ -117,9 +118,14 @@ def build_run_list(test, run_lines, verbose=False):
common.warn("Skipping unparsable RUN line: " + l)
continue
- commands = [cmd.strip() for cmd in l.split("|", 1)]
- llc_cmd = commands[0]
- filecheck_cmd = commands[1] if len(commands) > 1 else ""
+ commands = [cmd.strip() for cmd in l.split("|")]
+ assert len(commands) >= 2
+ preprocess_cmd = None
+ if len(commands) > 2:
+ preprocess_cmd = " | ".join(commands[:-2])
+
+ llc_cmd = commands[-2]
+ filecheck_cmd = commands[-1]
common.verify_filecheck_prefixes(filecheck_cmd)
if not llc_cmd.startswith("llc "):
@@ -145,7 +151,7 @@ def build_run_list(test, run_lines, verbose=False):
check_prefixes = common.get_check_prefixes(filecheck_cmd)
all_prefixes += check_prefixes
- run_list.append(Run(check_prefixes, cmd_args, triple))
+ run_list.append(Run(check_prefixes, cmd_args, preprocess_cmd, triple))
# Sort prefixes that are shared between run lines before unshared prefixes.
# This causes us to prefer printing shared prefixes.
@@ -358,11 +364,21 @@ def update_test_file(args, test, autogenerated_note):
for run in run_list:
for prefix in run.prefixes:
func_dict.update({prefix: dict()})
- for prefixes, llc_args, triple_in_cmd in run_list:
+ for prefixes, llc_args, preprocess_cmd, triple_in_cmd in run_list:
log("Extracted LLC cmd: llc {}".format(llc_args), args.verbose)
log("Extracted FileCheck prefixes: {}".format(prefixes), args.verbose)
- raw_tool_output = args.llc_binary(llc_args, test)
+ if test.endswith(".mir"):
+ ...
[truncated]
|
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| # RUN: sed 's/XLen/32/g' %s | llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=regbankselect \ | ||
| # RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs -x mir \ | ||
| # RUN: -o - | FileCheck %s --check-prefixes=CHECK-RV32 | ||
| # RUN: sed 's/XLen/64/g' %s | llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=regbankselect \ | ||
| # RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs -x mir \ | ||
| # RUN: -o - | FileCheck %s --check-prefixes=CHECK-RV64 |
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I think this is less maintainable than just duplicating the test. Does update_mir_test_checks even understand how to run the pre-sed command? It doesn't really parse and execute the command
Also really should have end to end IR tests. Pure mir tests are overused at this point
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I would some what agree that spliting the test up would be more reasonable but that only case in the the new fp-load-store.mir test required that sed replacement was the one I added so it seemed sad to force duplication for just 1 part of the test case. On the other hand if we keep the tests conjoined it makes sure RV32 and RV64 cannot diverge on register select for these simple cases which is probably better imo. @topperc asked me to keep them together maybe he had a different reason.
You are correct that the update__mir_test_checks did not (past tense :)) handle preprocessor commands however I added that to the python script using the same infra that the update_llc_test_checks script uses so the two of them converged a little bit which I think is a plus. I feel as though this is better as a MIR test because its directly testing the register select behavior that was changed. IR would of course test that in a full sweep but it would also be indirectly testing a bunch of different behaviors that might change in the future. Let me know what you think you guys are the bosses!
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Let's move it to an IR test. I only suggested the MIR test because that's where we had existing coverage for the regbank selection for FP load/store.
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Cool so I dropped the .mir test and script change and added a float-fclass.ll test |
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Signed-off-by: Luke Quinn <[email protected]>
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@lquinn2015 Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR. Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues. How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
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Bug fix FCLASS instruction in RISCV. The bug is due the fact that FCLASS has an input float register and output GPR this caused reg bank select regression.